SLLSF19 December   2017 TCAN4420

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Functional Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Power Supply Characteristics
    7. 6.7 AC and DC Electrical Characteristics
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 TXD Dominant Time Out (DTO)
      2. 8.3.2 CAN Bus Short Circuit Current Limiting
      3. 8.3.3 Thermal Shutdown
      4. 8.3.4 Under Voltage Lockout (UVLO) and Unpowered Device
        1. 8.3.4.1 VIO Supply PIN
    4. 8.4 Device Functional Modes
      1. 8.4.1 Polarity Configuration
      2. 8.4.2 Normal Polarity Mode
      3. 8.4.3 Reverse Polarity Mode
      4. 8.4.4 Driver and Receiver Function
      5. 8.4.5 Floating Terminals
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Bus Loading, Length and Number of Nodes
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CAN Termination
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Timing Requirements

MINNOMMAXUNIT
Switching Characteristics
tpHR Propagation delay time,
high TXD to Driver Recessive		 See Figure 9,
Typical Conditions for DS: RL = 60 Ω, CL = 100 pF, RCM = open		 50 ns
tpLD Propagation delay time,
low TXD to Driver Dominant		 40
tsk(p) Pulse skew (|tpHR - tpLD|) 10
tR Differential output signal rise time 25
tF Differential output signal fall time 25
tTXD_DTO Dominant time out(1) See Figure 13, RL = 60 Ω, CL = open 1.2 4 ms
tpRH Propagation delay time, bus recessive input to high RXD_INT output See Figure 10 CL(RXD) = 15 pF
Typical Conditions for DS: CANL = 1.5 V, CANH = 3.5 V		 50 ns
tpDL Propagation delay time, bus dominant input to RXD low output 50
tR Differential output signal rise time 8
tF Differential output signal fall time 8
Device Switching Characteristics
t(LOOP1) Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant(2) See Figure 10 Typical Conditions: RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF 150 ns
t(LOOP2) Total loop delay, driver input (TXD) to receiver output (RXD), dominant to receissive(2) See Figure 10 Typical Conditions: RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF 150
tMODE Mode change time from normal configuration to reverse 300 µs
tUV_RE-ENABLE Re-enable time after UV event See Figure 10. Time for device to return to normal operation from UVVCC and UVVIO under voltage event 300 µs
(1) The TXD dominant time out (tTXD_DTO) disables the driver of the transceiver once the TXD has been dominant longer than tTXD_DTO, which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the tTXD_DTO minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ tTXD_DTO = 11 bits / 1.2 ms = 9.2 kbps.
(2) Time span from signal edge on TXD input to next signal edge with same polarity on RXD output, the maximum of delay of both signal edges is to be considered.