SLLSEZ5 Data sheet

SLLSEZ5D January 2018 – June 2022 TCAN4550-Q1

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RGY|20
- MPQF116H

Thermal pad, mechanical data (Package|Pins)

RGY|20
- QFND734

Orderable Information

8.4.6.1 Watchdog Function

The TCAN4550-Q1 contains a watchdog (WD) timeout function. When using the WD timeout function, the WD runs continuously. The WD is default enabled and can be configured with four different timer values. WD is active in normal and standby modes and off in sleep mode. Once the device enters standby or normal mode, the timer does not start until the first input trigger event. This event can be either writing a one to register 16'h0800[18] or if selected, by changing the voltage level on the GPIO1 pin either high or low when configured for watchdog input. If the first trigger is not set, the watchdog is disabled. The first trigger can happen in standby mode or normal mode. This is system implementation specific. While the timer is running, a SPI command writing a one to 16'h0800[18] resets the WD_TIMER timer or if configured for pin control the GPIO1 behaves as the watchdog input bit.

The TCAN4550-Q1 has two ways of setting the trigger bit: via a SPI command and, if selected, through a GPI (GPIO1 configured as GPI). When a GPI pin is used any rising or falling edge resets the timer. A watchdog event can be conveyed back to the microprocessor in two methods: interrupt on nINT pin or, if selected, the GPO2 pin can be programmed to toggle upon a WD timeout. A timeout can initiate one of three actions by the TCAN4550-Q1: interrupt, INH toggle plus putting the device into standby mode or toggle watchdog output reset pin if enabled. The input CLKIN or crystal values needs to be entered into reg 16'h0800[27] and is either 20 MHz or 40 MHz. See Table 8-2 for the register settings for the watchdog function.

Note:

If the device enters UV_IO protected mode, the watchdog timer is held in reset. When the device returns to standby mode, the timer resumes counting.
Once the command to enter sleep mode takes place, the WD timer is turned off and does not trigger a watchdog event.
If the any of the watchdog registers needs to be changed, the watchdog must be disabled and the change made and then re-enabled.

Table 8-2 Watchdog Registers and Descriptions

Address	BIT(S)	Field	Type	Reset	DESCRIPTION
16'h0800	29:28	WD_TIMER	R/W	2'b00	WD_TIMER: Watchdog timer 00 = 60 ms 01 = 600 ms 10 = 3 s 11 = 6 s
	27	CLK_REF	R/W	1'b1	CLK_REF: CLKIN/Crystal frequency reference 0 = 20 MHz 1 = 40 MHz
	23:22	GPO2_CONFIG	R/W	2'b00	GPO2_CONFIG: GPO2 configuration 00 = No action 01 = M_CAN_INT 0 interrupt (active low) 10 = Watchdog output 11 = Mirrors nINT pin
	18	WD_BIT_SET	W1C	1'b0	WD_BIT_SET: write a 1 to reset timer: if times out; this bit is set and then the selected action from register 16'h0800[17:16] takes place. Note: This is a self-clearing bit. Writing a 1 resets the timer and then the bit clears.
	17:16	WD_ACTION	R/W	2'b00	WD_ACTION: Selected action when WD_TIMER times out 00 = Set interrupt flag and if a pin is configured to reflect WD output as an interrupt the pin shows a low. 01 = Pulse INH pin and place device into standby mode – high - low - high ≈300ms 10 = Pulse watchdog output pin if enabled – high - low - high ≈300ms 11 = Reserved Note: Interrupt flag is always set for a WD timeout event.
16'h0800	15:14	GPIO1_CONFIG	RW	2'b01	GPIO1_CONFIG: GPIO1 Pin Function Select 00 = GPO 01 = Reserved 10 = GPI – Automatically becomes a WD input trigger pin. 11 = Reserved
16'h0800	3	WD_EN	RXU	1'b1	WD_EN - Watchdog Enable 0 = Disable 1 = Enabled