SLLSEZ5D January 2018 – June 2022 TCAN4550-Q1
PRODUCTION DATA
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
WAKE_CONFIG | WD_TIMER | CLK_REF | RSVD | RSVD | RSVD | ||
R/W | R/W | R/W | R | R | R | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
GPO2_CONFIG | TEST_MODE_EN | RSVD | nWKRQ_VOLTAGE | WD_BIT_SET | WD_ACTION | ||
R/W | R/W | R | R/W | R/W | R/W | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GPIO1_CONFIG | FAIL_SAFE_EN | RSVD | GPIO1_GPO_CONFIG | INH_DIS | nWKRQ_CONFIG | ||
R/W | R/W | R | R/W | R/W | R/W | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODE_SEL | RSVD | RSVD | WD_EN | DEVICE_RESET | SWE_DIS | TEST_MODE_CONFIG | |
R/W/U | R | R | R/W/U | R/W/U | R/W | R/W |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:30 | WAKE_CONFIG | R/W | 2’b11 | WAKE_CONFIG: Wake pin configuration 00 = Disabled 01 = Rising edge 10 = Falling edge 11 = Bi-Directional – either edge |
29:28 | WD_TIMER | R/W | 2’b00 | WD_TIMER: Watchdog timer 00 = 60 ms 01 = 600 ms 10 = 3 s 11 = 6 s |
27 | CLK_REF | R/W | 1'b1 | CLK_REF: CLKIN/Crystal Frequency Reference 0 = 20 MHz 1 = 40 MHz |
26:24 | RSVD | R | 3'b000 | Reserved |
23:22 | GPO2_CONFIG | R/W | 2’b00 | GPO2_CONFIG: GPO2 Pin GPO Configuration 00 = No Action 01 = MCAN_INT 0 interrupt (Active low) 10 = Watchdog output 11 = Mirrors nINT pin (Active low) See NOTE section |
21 | TEST_MODE_EN | R/W | 1'b0 | TEST_MODE_EN: Test mode enable. When set device is in test mode 0 = Disabled 1 = Enabled |
20 | RSVD | R | 1'b0 | Reserved |
19 | nWKRQ_VOLTAGE | R/W | 1’b0 | nWKRQ_VOLTAGE: nWKRQ Pin GPO buffer voltage rail
configuration: 0 = Internal voltage rail 1 = VIO voltage rail |
18 | WD_BIT_SET | R/W | 1’b0 | WD_BIT_SET: Write a 1 to reset timer: if times out, this bit will set and then the selected action from 0800[17:16] will take place. (TCAN4x50 Only otherwise reserved) This is a self-clearing bit. Writing a 1 resets the timer and then the bit clears |
17:16 | WD_ACTION | R/W | 2’b00 | WD_ACTION: Selected action when WD_TIMER times out 00 = Set interrupt flag, and if a pin is configure to reflect WD output as an interrupt the pin will show a low. 01 = Pulse INH pin and places the device into standby mode – high to low to high ≈300 ms 10 = Pulse watchdog output pin if enabled – high to low to high ≈300 ms 11 = Reserved NOTE: Interrupt flag is always set for a WD timeout event. |
15:14 | GPIO1_CONFIG | R/W | 2’b00 | GPIO1_CONFIG: GPIO1 Pin Function Select 00 = GPO 01 = Reserved 10 = GPI – Automatically becomes a WD input trigger pin. 11 = Reserved |
13 | FAIL_SAFE_EN | R/W | 1'b0 | FAIL_SAFE_EN: Fail safe mode enable: 0 = Disabled 1 = Enabled NOTE: Excludes power up fail safe. |
12 | RSVD | R | 1'b0 | Reserved |
11:10 | GPIO1_GPO_CONFIG | R/W | 2’b01 | GPIO1_GPO_CONFIG: GPIO1 pin GPO1 function select 00 = SPI fault Interrupt (Active low) 01 = MCAN_INT 1 (Active low) 10 = Under voltage or thermal event interrupt (Active low) 11 = Reserved |
9 | INH_DIS | R/W | 1'b0 | INH_DIS: INH Pin Disable 0 = Pin enabled 1 = Pin disabled |
8 | nWKRQ_CONFIG | R/W | 1'b0 | nWKRQ_CONFIG: nWKRQ Pin Function 0 = Mirrors INH function 1 = Wake request interrupt |
7:6 | MODE_SEL | R/W | 2'b01 | MODE_SEL: Mode of operation select 00 = Sleep 01 = Standby 10 = Normal 11 = Reserved See NOTE section |
5 | RSVD | R | 1'b1 | If this bit is written to it must be a 1 |
4 | RSVD | R | 1'b0 | Reserved |
3 | WD_EN | R/X/U | 1’b1 | WD_EN: Watchdog Enable 0 = Disabled 1 = Enabled |
2 | DEVICE_RESET | R/WC | 1'b0 | DEVICE_RESET: Device Reset 0 = Current configuration 1 = Device resets to default NOTE: Same function as RST pin |
1 | SWE_DIS | R/W | 1'b0 | SWE_DIS: Sleep Wake Error Disable: 0 = Enabled 1 = Disabled NOTE: This disables the device from starting the four-minute timer when coming out of sleep mode on a wake event. If this is enabled, a SPI read or write must take place within this four minute window or the device will go back to sleep. This does not disable the function for initial power on or in case of a power on reset. |
0 | TEST_MODE_CONFIG | R/W | 1'b0 | Test Mode Configuration 0 = Phy Test with TXD/RXD_INT_PHY and EN_INT are mapped to external pins 1 = CAN Controller test with TXD/RXD_INT_CAN mapped to external pins |