SLLSEZ5D January 2018 – June 2022 TCAN4550-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS (1) | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| CAN DRIVER ELECTRICAL CHARACTERISTICS | ||||||
| VO(D) | Bus output voltage (dominant) CANH | See Figure 7-3 and Figure 7-4, TXD_INT = 0 V, EN = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open | 2.75 | 4.5 | V | |
| Bus output voltage (dominant) CANL | 0.5 | 2.25 | V | |||
| VO(R) | Bus output voltage (recessive) | See Figure 7-1 and Figure 7-4, TXD_INT = VIO, RL = open (no load), RCM = open | 2 | 2.5 | 3 | V |
| V(DIFF) | Maximum differential voltage rating | See Figure 7-1 and Figure 7-4 | –5.0 | 10 | V | |
| VO(STB) | Bus output voltage (Standby Mode) CANH | See Figure 7-1 and Figure 7-4, TXD_INT = VIO, RL = open (no load), RCM = open | –0.1 | 0.1 | V | |
| Bus output voltage (Standby Mode) CANL | –0.1 | 0.1 | V | |||
| Bus output voltage (Standby Mode) CANH - CANL | –0.2 | 0.2 | V | |||
| VOD(D) | Differential output voltage (dominant) | See Figure 7-1 and Figure 7-4, TXD_INT = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open | 1.5 | 3 | V | |
| See Figure 7-1 and Figure 7-4, TXD_INT = 0 V, 45 Ω ≤ RL ≤ 70 Ω, CL = open, RCM = open | 1.4 | 3 | V | |||
| See Figure 7-1 and Figure 7-4, TXD_INT = 0 V, RL = 2.24 kΩ, CL = open, RCM = open | 1.5 | 5 | V | |||
| VOD(R) | Differential output voltage (recessive) | See Figure 7-1 and Figure 7-4, TXD_INT = VIO, RL = 60 Ω, CL = open, RCM = open | –120 | 12 | mV | |
| See Figure 7-1 and Figure 7-4, TXD_INT = VIO, RL = open (no load), CL = open, RCM = open | –50 | 50 | mV | |||
| VSYM | Output
symmetry (dominant or recessive) ( VO(CANH) + VO(CANL)) / VCC |
See Figure 7-1 and Figure 7-4, RL = 60 Ω, CL = open, RCM = open, C1 = 4.7 nF, TXD_INT - 250 kHZ, 1 MHz | 0.9 | 1.1 | V/V | |
| VSYM_DC | Output symmetry (dominant or recessive) (VCC – VO(CANH) – VO(CANL)) with a frequency that corresponds to the highest bit rate for which the HS-PMA implementation is intended, however, at most 1 MHz (2 Mbit/s) | See Figure 7-1 and Figure 7-4, RL = 60 Ω, CL = open, RCM = open, C1 = 4.7 nF | –300 | 300 | mV | |
| IOS_DOM | Short-circuit steady-state output current, dominant | See Figure 7-1 and Figure 7-8, -3.0 V ≤ VCANH ≤ 18.0 V, CANL = open, TXD_INT = 0 V | –100 | mA | ||
| See Figure 7-1 and Figure 7-8, -3.0 V ≤ VCANL ≤+18.0 V, CANH = open, TXD_INT = 0 V | 100 | mA | ||||
| IOS_REC | Short-circuit steady-state output current, recessive | See Figure 7-1 and Figure 7-8, – 27 V ≤ VBUS ≤ 32 V, VBUS = CANH = CANL | –5 | 5 | mA | |
| CAN RECEIVER ELECTRICAL CHARACTERISTICS | ||||||
| VITdom | Receiver dominant state differential input voltage range, bus biasing active | -12.0 V ≤ VCANL ≤ +12.0 V -12.0 V ≤ VCANH ≤ +12.0 V See Figure 7-5, Table 8-3 |
0.9 | 8 | V | |
| VITrec | Receiver recessive state differential input voltage range bus biasing active | –3.0 | 0.5 | V | ||
| VHYS | Hysteresis voltage for input-threshold, normal modes | See Figure 7-5, Table 8-3 | 120 | mV | ||
| VIT(ENdom) | Receiver dominant state differential input voltage range, bus biasing inactive (VDiff) | -12.0 V ≤
VCANL ≤ +12.0 V -12.0 V ≤ VCANH ≤ +12.0 V See Figure 7-5, Table 8-3 |
1.15 | 8 | V | |
| VIT(ENrec) | Receiver recessive state differential input voltage range, bus biasing inactive (VDiff) | -12.0 V ≤
VCANL ≤ +12.0 V -12.0 V ≤ VCANH ≤ +12.0 V See Figure 7-5, Table 8-3 |
–3 | 0.4 | V | |
| VCM | Common mode range: normal | See Figure 7-5, Table 8-3 | –12 | 12 | V | |
| VCM(EN) | Common mode range: standby mode | See Figure 7-5, Table 8-3 | –12 | 12 | V | |
| IIOFF(LKG) | Power-off (unpowered) bus input leakage current | VCANH = VCANL = 5 V, Vsup to GND via 0 Ω and 47 kΩ resistor | 5 | µA | ||
| CI | Input capacitance to ground (CANH or CANL) | 25 | pF | |||
| CID | Differential input capacitance | 14 | pF | |||
| RID | Differential input resistance | TXD_INT = VCCINT, normal mode: -2.0 V ≤ VCANH ≤+7.0 V; -2.0 V ≤VCANL ≤ + 7.0 V | 60 | 100 | kΩ | |
| RIN | Single ended Input resistance (CANH or CANL) | -2.0 V ≤ VCANH ≤+7.0 V; -2.0 V ≤VCANL ≤ + 7.0 V | 30 | 50 | kΩ | |
| RIN(M) | Input resistance matching: [1 – (RIN(CANH) / (RIN(CANL))] × 100% | VCANH = VCANL = 5.0 V | –1 | 1 | % | |
| VCCOUT SUPPLY TERMINAL | ||||||
| VCCOUT | 5 V output supply | ICCOUT = -70 mA to 0 mA; VSUP = 5.5 V to 18 V; -40°C < TA < 85°C | 4.75 | 5 | 5.25 | V |
| VDROP | Drop out voltage | VCCOUT = 5 V, VSUP = 12 V, ICCOUT = 70 mA | 300 | 500 | mV | |
| ΔVCC(ΔVSUP) | Line regulation | VSUP = 5.5 V to 30 V, ΔVCCOUT, ICCOUT = 10 mA | 50 | mV | ||
| ΔVCC(ΔVSUPL) | Load regulation | VSUP = 14 V, ICCOUT = 1 mA to 70 mA, ΔVCCOUT, –40℃ ≤ TA ≤ 125℃ | 60 | mV | ||
| UVCCOUT | Under voltage threshold on VCCOUT | 4.2 | 4.55 | V | ||
| FLTR TERMINAL | ||||||
| VMEASURE | Voltage measured at FLTR pin | 1.5 | V | |||
| C(FLTR) | Filter pin capacitor | External filter capacitor | 300 | 330 | nF | |
| INH OUTPUT TERMINAL (HIGH VOLTAGE OUTPUT) | ||||||
| ΔVH | High-level voltage drop INH with respect to VSUP | IINH = - 0.5 mA | 0.5 | 1 | V | |
| ILKG(INH) | Leakage current | INH = 0 V, Sleep Mode | –0.5 | 0.7 | µA | |
| WAKE INPUT TERMINAL (HIGH VOLTAGE INPUT) | ||||||
| VIH | High-level input voltage | Standby mode, WAKE pin enabled | VSUP–2 | V | ||
| VIL | Low-level input voltage | Standby mode, WAKE pin enabled | VSUP–3 | V | ||
| IIH | High-level input current | WAKE = VSUP–1 V | –25 | –15 | µA | |
| IIL | Low-level input current | WAKE = 1 V | 15 | 25 | µA | |
| tWAKE | WAKE filter time | Wake up filter time from a wake edge on WAKE; standby, sleep mode | 50 | µs | ||
| SDI, SCK, GPIO1 INPUT TERMINALS | ||||||
| VIH | High-level input voltage | 0.7 | VIO | |||
| VIL | Low-level input voltage | 0.3 | VIO | |||
| IIH | High-level input leakage current | Inputs = VIO = 5.25 V | –1 | 1 | µA | |
| IIL | Low-level input leakage current | Inputs = 0 V, VIO = 5.25 V | –100 | –5 | µA | |
| CIN | Input capacitance | 18 MHz | 10 | 12 | pF | |
| ILKG(OFF) | Unpowered leakage current (SDI and SCK only) | Inputs = 5.25 V, VIO = VSUP = 0 V | –1 | 1 | µA | |
| nCS INPUT TERMINAL | ||||||
| VIH | High-level input voltage | 0.7 | VIO | |||
| VIL | Low-level input voltage | 0.3 | VIO | |||
| IIH | High-level input leakage current | nCS = VIO = 5.25 V | –1 | 1 | µA | |
| IIL | Low-level input leakage current | nCS = VIO = 5.25 V | –50 | –5 | µA | |
| ILKG(OFF) | Unpowered leakage current | nCS = 5.25 V, VIO = VSUP = 0 V | –1 | 1 | µA | |
| RST INPUT TERMINAL | ||||||
| VIH | High-level input voltage | 0.7 | VIO | |||
| VIL | Low-level input voltage | 0.3 | VIO | |||
| IIH | High-level input leakage current | RST = VIO = 5.25 V | 1 | 10 | µA | |
| IIL | Low-level input leakage current | RST = 0 V | –1 | 1 | µA | |
| ILKG(OFF) | Unpowered leakage current | RST = VIO, VSUP = 0 V | –7.5 | 7.5 | µA | |
| tPULSE_WIDTH | Width of the input pulse | 30 | µs | |||
| SDO, GPIO1, GPO2 OUTPUT TERMINAL; nINT (OPEN DRAIIN) and nWKRQ (WHEN PROGRAMMED TO WORK OFF OF VIO AND IS OPEN DRAIN) | ||||||
| VOH | High-level output voltage | 0.8 | VIO | |||
| VOL | Low-level output voltage | 0.2 | VIO | |||
| nWKRQ OUTPUT TERMINAL (DEFAULT INTERNAL VOLTAGE RAIL) | ||||||
| VOH | High-level output voltage | Default value when based upon internal voltage rail | 2.8 | 3.6 | V | |
| VOL | Low-level output voltage | Default value when based upon internal voltage rail | 0.7 | V | ||
| OSC1 TERMINAL AND CRYSTAL SPECIFICATION | ||||||
| VIH | High-level input voltage | 0.85 | 1.10 | VIO | ||
| VIL | Low-level input voltage | 0.3 | VIO | |||
| FOSC1 | Clock-In frequency tolerance , see section Section 9.1.1 | 20 MHz | –0.5 | 0.5 | % | |
| FOSC1 | Clock-In frequency tolerance, see section Section 9.1.1 | 40 MHz | –0.5 | 0.5 | % | |
| tDC | Input duty cycle | 45 | 55 | % | ||
| ESR | Crystal ESR for load capacitance (2) | 60 | Ω | |||