SLLSEZ5 Data sheet

SLLSEZ5D January 2018 – June 2022 TCAN4550-Q1

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RGY|20
- MPQF116H

Thermal pad, mechanical data (Package|Pins)

RGY|20
- QFND734

Orderable Information

6.9 Switching Characteristics

over operating free-air temperature range for – 40 ℃ ≤ T_A ≤ 125 ℃ (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SWITCHING CHARACTERISTICS (CAN TRANSCEIVER ONLY)
t_pHR	Propagation delay time, high TXD_INT to Driver Recessive ⁽¹⁾	See Figure 7-4, RST = 0 V. Typical conditions: R_L = 60 Ω, C_L = 100 pF, R_CM = open	50	85	110	ns
t_pLD	Propagation delay time, low TXD_INT to driver dominant ⁽¹⁾		35	75	100	ns
t_sk(p)	Pulse skew (\|t_pHR – t_pLD\|)			30	40	ns
t_R/F	Differential output signal rise time:		8	55	75	ns
t_pRH	Propagation delay time, bus recessive input to high RXD_INT output	See Figure 7-5, typical conditions: CANL = 1.5 V, CANH = 3.5 V.	35	55	90	ns
t_pDL	Propagation delay time, bus dominant input to RXD_INT low output		35	55	90	ns
DEVICE SWITCHING CHARACTERISTICS
t_LOOP	Loop delay⁽³⁾(CAN transceiver only)	See Figure 7-6, RST = 0 V. typical conditions: R_L = 60 Ω, C_L = 100 pF, C_RXD = 15 pF			235	ns
t_{WK_FILTER}	Bus time to meet filtered bus requirements for wake up request	See Figure 8-6, standby mode.	0.5		1.8	µs
t_{WK_TIMEOUT}	Bus wake-up timeout: time that a WUP must take place within to be considered valid	See Figure 8-6	0.5		2.9	ms
t_SILENCE	Timeout for bus inactivity ⁽⁶⁾	Timer is reset and restarted when bus changes from dominant to recessive or vice versa.	0.6		1.2	s
t_INACTIVE	Time required for the processor to clear wake flag or put the device into normal mode upon power up, power on reset or after wake event otherwise the device will enter sleep mode ⁽⁶⁾		2	4	6	min
t_Bias	Time from the start of a dominant-recessive-dominant sequence	Each phase 6 µs until V_sym ≥ 0.1. See Figure 7-10			250	µs
t_{Power_Up}	Power up time on V_SUP ⁽⁶⁾	See Figure 7-13			250	µs
t_{TXD_INT_DTO}	Dominant time out⁽²⁾ (CAN transceiver only)⁽¹⁾	See Figure 8-7, R_L = 60 Ω, C_L = open	1		5	ms
TRANSMITTER AND RECEIVER SWITCHING CHARACTERISTICS
t_Bit(Bus)2M	Transmitted recessive bit width @ 2 Mbps	See Figure 7-5, RST = 0 V typical conditions: R_L = 60 Ω, C_L = 100 pF, C_RXD = 15 pF	435		530	ns
t_Bit(Bus)5M	Transmitted recessive bit width @ 5 Mbps		155		210	ns
t_Bit(Bus)8M ⁽⁵⁾	Transmitted recessive bit width @ 8 Mbps	See Figure 7-5, RST = 0 V typical conditions: R_L = 60 Ω, C_L = 100 pF, C_RXD = 15 pF	80		135	ns
t_Bit(RXD)2M	Received recessive bit width @ 2 Mbps	See Figure 7-5, RST = 0 V typical conditions: R_L = 60 Ω, C_L = 100 pF, C_RXD = 15 pF,	400		550	ns
t_Bit(RXD)5M	Received recessive bit width @ 5 Mbps		120		220	ns
t_Bit(RXD)8M ⁽⁵⁾	Received recessive bit width @ 8 Mbps	See Figure 7-5, RST = 0 V typical conditions: R_L = 60 Ω, C_L = 100 pF, C_RXD = 15 pF	80		135	ns
Δt_Rec ⁽⁴⁾	Receiver Timing symmetry @ 2 Mbps	See Figure 7-5, RST = 0 V typical conditions: R_L = 60 Ω, C_L = 100 pF, C_RXD = 15 pF	–65	30	40	ns
Δt_Rec ⁽⁴⁾	Receiver Timing symmetry @ 5 Mbps		–45	5	15	ns
SPI SWITCHING CHARACTERISTICS
f_SCK	SCK, SPI clock frequency ⁽⁶⁾				18	MHz
t_SCK	SCK, SPI clock period ⁽⁶⁾	See Figure 7-12	56			ns
t_RSCK	SCK rise time ⁽⁶⁾	See Figure 7-11			10	ns
t_FSCK	SCK fall time ⁽⁶⁾	See Figure 7-11			10	ns
t_SCKH	SCK, SPI clock high ⁽⁶⁾	See Figure 7-12	18			ns
t_SCKL	SCK, SPI clock low ⁽⁶⁾	See Figure 7-12	18			ns
t_CSS	Chip select setup time ⁽⁶⁾	See Figure 7-11	28			ns
t_CSH	Chip select hold time ⁽⁶⁾	See Figure 7-11	28			ns
t_CSD	Chip select disable time ⁽⁶⁾	See Figure 7-11	125			ns
t_SISU	Data in setup time ⁽⁶⁾	See Figure 7-11	5			ns
t_SIH	Data in hold time ⁽⁶⁾	See Figure 7-11	10			ns
t_SOV	Data out valid ⁽⁶⁾	V_IO = 3.135 V to 5.25 V, See Figure 7-12			20	ns
t_RSO	SO rise time ⁽⁶⁾	See Figure 7-12			10	ns
t_FSO	SO fall time ⁽⁶⁾	See Figure 7-12			10	ns

(1) All TXD_INT, RXD_INT, EN_INT and CAN transceiver only references are for internal nodes that represent the same functions for a stand-alone transceiver.

(2) The TXD_INT dominant time out (t_{TXD_INT_DTO}) disables the driver of the transceiver once the TXD_INT has been dominant longer than t_{TXD_INT_DTO}, which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after TXD_INT has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD_INT) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the t_{TXD_INT_DTO} minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ t_{TXD_INT_DTO} = 11 bits / 1.2 ms = 9.2 kbps.

(3) Time span from signal edge on TXD_INT input to next signal edge with same polarity on RXD output, the maximum of delay of both signal edges is to be considered.

(4) Δt_Rec = t_Bit(RXD) – t_Bit(Bus)

(5) Characterized but not 100% tested

(6) Specified by design