SLLSF91A December 2018 – January 2020 TCAN4550
PRODUCTION DATA.
The MRAM and start address for this register, F0SA, has special consideration.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
F0OM | F0WM[6:0] | ||||||
RP | RP | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RSVD | F0S[6:0] | ||||||
R | RP | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
F0SA[15:8] | |||||||
RP | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
F0SA[7:0] | |||||||
RP |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | F0OM | RP | 0 | FIFO 0 Operation Mode
FIFO 0 can be operated in blocking or in overwrite mode 0 - FIFO 0 blocking mode 1 - FIFO 0 overwrite mode |
32:24 | F0WM[6:0] | RP | 0x0 | Rx FIFO 0 Watermark
0 - Watermark interrupt disabled 1-64 - Level for Rx FIFO 0 watermark interrupt (IR.RF0W) >64 - Watermark interrupt disabled |
23 | RSVD | R | 0 | Reserved |
22:16 | F0S[6:0] | RP | 0x0 | Rx FIFO 0 Size
0 - No Rx FIFO 0 1-64 - Number of Rx FIFO 0 elements >64 - Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to F0S-1 |
15:0 | F0SA[15:0] | RP | 0x00 | Rx FIFO 0 Start Address
Start address of Rx FIFO 0 in Message RAM |