SLLSEZ4A August   2019  – November 2019 TCAN4551-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematics, CLKIN from MCU
      2.      Simplified Schematics, Crystal
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings, IEC ESD and ISO Transient Specification
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Supply Characteristics
    7. 6.7  Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VSUP Pin
      2. 8.3.2  VIO Pin
      3. 8.3.3  GND
      4. 8.3.4  INH Pin
      5. 8.3.5  WAKE Pin
      6. 8.3.6  FLTR Pin
      7. 8.3.7  VCCFLTR Pin
      8. 8.3.8  RST Pin
      9. 8.3.9  OSC1 and OSC2 Pins
      10. 8.3.10 nWKRQ Pin
      11. 8.3.11 nINT Interrupt Pin
      12. 8.3.12 GPO1 Pin
      13. 8.3.13 GPO2 Pin
      14. 8.3.14 CANH and CANL Bus Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Sleep Mode
        1. 8.4.3.1 Bus Wake via RXD_INT Request (BWRR) in Sleep Mode
        2. 8.4.3.2 Local Wake Up (LWU) via WAKE Input Terminal
      4. 8.4.4 Test Mode
      5. 8.4.5 Failsafe Feature
      6. 8.4.6 Protection Features
        1. 8.4.6.1 Driver and Receiver Function
        2. 8.4.6.2 Floating Terminals
        3. 8.4.6.3 TXD_INT Dominant Timeout (DTO)
        4. 8.4.6.4 CAN Bus Short Circuit Current Limiting
        5. 8.4.6.5 Thermal Shutdown
        6. 8.4.6.6 Under Voltage Lockout (UVLO) and Unpowered Device
          1. 8.4.6.6.1 UVSUP and UVCCFLTR
          2. 8.4.6.6.2 Fault and M_CAN Core Behavior:
      7. 8.4.7 CAN FD
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 Chip Select Not (nCS):
        2. 8.5.1.2 SPI Clock Input (SCLK):
        3. 8.5.1.3 SPI Data Input (SDI):
        4. 8.5.1.4 SPI Data Output (SDO):
      2. 8.5.2 Register Descriptions
    6. 8.6 Register Maps
      1. 8.6.1 Device ID and Interrupt/Diagnostic Flag Registers: 16'h0000 to 16'h002F
        1. 8.6.1.1 DEVICE_ID1[31:0] (address = h0000) [reset = h4E414354]
          1. Table 9. Device ID Field Descriptions
        2. 8.6.1.2 DEVICE_ID2[31:0] (address = h0004) [reset = h31353534]
          1. Table 10. Device ID Field Descriptions
        3. 8.6.1.3 Revision (address = h0008) [reset = h00110201]
          1. Table 11. Revision Field Descriptions
        4. 8.6.1.4 Status (address = h000C) [reset = h0000000U]
          1. Table 12. Status Field Descriptions
      2. 8.6.2 Device Configuration Registers: 16'h0800 to 16'h08FF
        1. 8.6.2.1 Modes of Operation and Pin Configuration Registers (address = h0800) [reset = hC8000460]
          1. Table 14. Modes of Operation and Pin Configuration Registers Field Descriptions
        2. 8.6.2.2 Timestamp Prescalar (address = h0804) [reset = h00000002]
          1. Table 15. EMC Enhancement and Timestamp Prescalar Field Descriptions
        3. 8.6.2.3 Test Register and Scratch Pad (address = h0808) [reset = h00000000]
          1. Table 16. Test and Scratch Pad Register Field Descriptions
        4. 8.6.2.4 Test Register (address = h080C) [reset = h00000000]
          1. Table 17. Test Register Field Descriptions
      3. 8.6.3 Interrupt/Diagnostic Flag and Enable Flag Registers: 16'h0820/0824 and 16'h0830
        1. 8.6.3.1 Interrupts (address = h0820) [reset = h00100000]
          1. Table 18. Interrupts Field Descriptions
        2. 8.6.3.2 MCAN Interrupts (address = h0824) [reset = h00000000]
          1. Table 19. MCAN Interrupts Field Descriptions
        3. 8.6.3.3 Interrupt Enables (address = h0830 ) [reset = hFFFFFFFF]
          1. Table 20. Interrupt Enables Field Descriptions
      4. 8.6.4 CAN FD Register Set: 16'h1000 to 16'h10FF
        1. 8.6.4.1  Core Release Register (address = h1000) [reset = hrrrddddd]
          1. Table 24. Core Release Register Field Descriptions
        2. 8.6.4.2  Endian Register (address = h1004) [reset = h87654321]
          1. Table 25. Endian Register Field Descriptions
        3. 8.6.4.3  Customer Register (address = h1008) [reset = h00000000]
          1. Table 26. Customer Register Field Descriptions
        4. 8.6.4.4  Data Bit Timing & Prescaler (address = h100C) [reset = h0000A33]
          1. Table 27. Data Bit Timing & Prescaler Field Descriptions
        5. 8.6.4.5  Test Register (address = h1010 ) [reset = h00000000]
          1. Table 28. Test Register Field Descriptions
        6. 8.6.4.6  RAM Watchdog (address = h1014) [reset = h00000000]
          1. Table 29. RAM Watchdog Field Descriptions
        7. 8.6.4.7  Control Register (address = h1018) [reset = 0000 0019]
          1. Table 30. Control Register Field Descriptions
        8. 8.6.4.8  Nominal Bit Timing & Prescaler Register (address = h101C) [reset = h06000A03]
          1. Table 31. Nominal Bit Timing & Prescaler Register Field Descriptions
        9. 8.6.4.9  Timestamp Counter Configuration (address = h1020) [reset = h00000000]
          1. Table 32. Timestamp Counter Configuration Descriptions
        10. 8.6.4.10 Timestamp Counter Value (address = h1024) [reset = h00000000]
          1. Table 33. Timestamp Counter Value Field Descriptions
        11. 8.6.4.11 Timeout Counter Configuration (address = h1028) [reset = hFFFF0000]
          1. Table 34. Timeout Counter Configuration Field Descriptions
        12. 8.6.4.12 Timeout Counter Value (address = h102C) [reset = h0000FFFF]
          1. Table 35. Timeout Counter Value Field Descriptions
        13. 8.6.4.13 Reserved (address = h1030 - h103C) [reset = h00000000]
          1. Table 36. Reserved Field Descriptions
        14. 8.6.4.14 Error Counter Register (address = h1040) [reset = h00000000]
          1. Table 37. Error Counter Register Field Descriptions
        15. 8.6.4.15 Protocol Status Register (address = h1044) [reset = h00000707]
          1. Table 38. Protocol Status Register Field Descriptions
        16. 8.6.4.16 Transmitter Delay Compensation Register (address = h1048) [reset = h00000000]
          1. Table 39. Transmitter Delay Compensation Register Field Descriptions
        17. 8.6.4.17 Reserved (address = h104C) [reset = h00000000]
          1. Table 40. Reserved Field Descriptions
        18. 8.6.4.18 Interrupt Register (address = h1050) [reset = h00000000]
          1. Table 41. Interrupt Register Field Descriptions
        19. 8.6.4.19 Interrupt Enable (address = h1054) [reset = h00000000]
          1. Table 42. Interrupt Enable Field Descriptions
        20. 8.6.4.20 Interrupt Line Select (address = h1058) [reset = h00000000]
          1. Table 43. Interrupt Line Select Field Descriptions
        21. 8.6.4.21 Interrupt Line Enable (address = h105C) [reset = h00000000]
          1. Table 44. Interrupt Line Enable Field Descriptions
        22. 8.6.4.22 Reserved (address = h1060 - h107C) [reset = h00000000]
          1. Table 45. Reserved Field Descriptions
        23. 8.6.4.23 Global Filter Configuration (address = h1080) [reset = h00000000]
          1. Table 46. Global Filter Configuration Field Descriptions
        24. 8.6.4.24 Standard ID Filter Configuration (address = h1084) [reset = h00000000]
          1. Table 47. Standard ID Filter Configuration Field Descriptions
        25. 8.6.4.25 Extended ID Filter Configuration (address = h1088) [reset = h00000000]
          1. Table 48. Extended ID Filter Configuration Field Descriptions
        26. 8.6.4.26 Reserved (address = h108C) [reset = h00000000]
          1. Table 49. Reserved Field Descriptions
        27. 8.6.4.27 Extended ID AND Mask (address = h1090) [reset = h1FFFFFFF]
          1. Table 50. Extended ID AND Mask Field Descriptions
        28. 8.6.4.28 High Priority Message Status (address = h1094) [reset = h00000000]
          1. Table 51. High Priority Message Status Field Descriptions
        29. 8.6.4.29 New Data 1 (address = h1098) [reset = h00000000]
          1. Table 52. New Data 1 Field Descriptions
        30. 8.6.4.30 New Data 2 (address = h109C) [reset = h00000000]
          1. Table 53. New Data 2 Field Descriptions
        31. 8.6.4.31 Rx FIFO 0 Configuration (address = h10A0) [reset = h00000000]
          1. Table 54. Rx FIFO 0 Configuration Field Descriptions
        32. 8.6.4.32 Rx FIFO 0 Status (address = h10A4) [reset = h00000000]
          1. Table 55. Rx FIFO 0 Status Field Descriptions
        33. 8.6.4.33 Rx FIFO 0 Acknowledge (address = h10A8) [reset = h00000000]
          1. Table 56. Rx FIFO 0 Acknowledge Field Descriptions
        34. 8.6.4.34 Rx Buffer Configuration (address = h10AC) [reset = h00000000]
          1. Table 57. Rx Buffer Configuration Field Descriptions
        35. 8.6.4.35 Rx FIFO 1 Configuration (address = h10B0) [reset = h00000000]
          1. Table 58. Rx FIFO 1 Configuration Field Descriptions
        36. 8.6.4.36 Rx FIFO 1 Status (address = h10B4) [reset = h00000000]
          1. Table 59. Rx FIFO 1 Status Field Descriptions
        37. 8.6.4.37 Rx FIFO 1 Acknowledge (address = h10B8) [reset = h00000000]
          1. Table 60. Rx FIFO 1 Acknowledge Field Descriptions
        38. 8.6.4.38 Rx Buffer/FIFO Element Size Configuration (address = h10BC) [reset = h00000000]
          1. Table 61. Rx Buffer/FIFO Element Size Configuration Field Descriptions
        39. 8.6.4.39 Tx Buffer Configuration (address = h10C0) [reset = h00000000]
          1. Table 62. Tx Buffer Configuration Field Descriptions
        40. 8.6.4.40 Tx FIFO/Queue Status (address = h10C4) [reset = h00000000]
          1. Table 63. Tx FIFO/Queue Status Field Descriptions
        41. 8.6.4.41 Tx Buffer Element Size Configuration (address = h10C8) [reset = h00000000]
          1. Table 64. Tx Buffer Element Size Configuration Field Descriptions
        42. 8.6.4.42 Tx Buffer Request Pending (address = h10CC) [reset = h00000000]
          1. Table 65. Tx Buffer Request Pending Field Descriptions
        43. 8.6.4.43 Tx Buffer Add Request (address = h10D0) [reset = h00000000]
          1. Table 66.   Tx Buffer Add Request Field Descriptions
          2. 8.6.4.43.1  Tx Buffer Cancellation Request (address = h10D4 [reset = h00000000]
            1. Table 67. Tx Buffer Cancellation Request Field Descriptions
          3. 8.6.4.43.2  Tx Buffer Add Request Transmission Occurred (address = h10D8) [reset = h00000000]
            1. Table 68. Tx Buffer Add Request Transmission Occurred Field Descriptions
          4. 8.6.4.43.3  Tx Buffer Cancellation Finished (address = h10DC) [reset = h00000000]
            1. Table 69. Tx Buffer Cancellation Finished Field Descriptions
          5. 8.6.4.43.4  Tx Buffer Transmission Interrupt Enable (address = h10E0) [reset = h00000000]
            1. Table 70. Tx Buffer Transmission Interrupt Enable Field Descriptions
          6. 8.6.4.43.5  Tx Buffer Cancellation Finished Interrupt Enable (address = h10E4) [reset = h00000000]
            1. Table 71. Tx Buffer Cancellation Finished Interrupt Enable Field Descriptions
          7. 8.6.4.43.6  Reserved (address = h10E8) [reset = h00000000]
            1. Table 72. Reserved Field Descriptions
          8. 8.6.4.43.7  Reserved (address = h10EC) [reset = h00000000]
            1. Table 73. Reserved Field Descriptions
          9. 8.6.4.43.8  Tx Event FIFO Configuration (address = h10F0) [reset = h00000000]
            1. Table 74. Tx Event FIFO Configuration Field Descriptions
          10. 8.6.4.43.9  Tx Event FIFO Status (address = h10F4) [reset = h00000000]
            1. Table 75. Tx Event FIFO Status Field Descriptions
          11. 8.6.4.43.10 Tx Event FIFO Acknowledge (address = h10F8) [reset = h00000000]
            1. Table 76. Tx Event FIFO Acknowledge Field Descriptions
          12. 8.6.4.43.11 Reserved (address = h10FC) [reset = h00000000]
            1. Table 77. Reserved Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Design Consideration
      1. 9.1.1 Crystal and Clock Input Requirements
      2. 9.1.2 Bus Loading, Length and Number of Nodes
      3. 9.1.3 CAN Termination
        1. 9.1.3.1 Termination
        2. 9.1.3.2 CAN Bus Biasing
      4. 9.1.4 INH Brownout Behavior
    2. 9.2 Typical Application
      1. 9.2.1 Detailed Requirements
      2. 9.2.2 Detailed Design Procedures
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
        1. 12.1.1.1 CAN Transceiver Physical Layer Standards:
        2. 12.1.1.2 EMC requirements:
        3. 12.1.1.3 Conformance Test requirements:
        4. 12.1.1.4 Community Resource
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.3.1 Interrupts (address = h0820) [reset = h00100000]

Figure 44. Interrupts
31 30 29 28 27 26 25 24
CANBUSNOM RSVD RSVD RSVD RSVD RSVD RSVD RSVD
RU R R R R R R R
23 22 21 20 19 18 17 16
RSVD UVSUP RSVD PWRON TSD RSVD RSVD ECCERR
R R/WC R R/WC/U R/WC R R R/WC
15 14 13 12 11 10 9 8
CANINT LWU WKERR RSVD RSVD CANSLNT RSVD CANDOM
R/WC R/WC R/WC R R R/WC R R/WC
7 6 5 4 3 2 1 0
GLOBALERR nWKRQ CANERR RSVD SPIERR RSVD M_CAN_INT VTWD
R R R R R R R R

Table 18. Interrupts Field Descriptions

Bit Field Type Reset Description
31 CANBUSNOM RU 1'b0 CAN Bus normal (Flag and Not Interrupt)
Will change to 1 when in normal mode after first Dom to Rec transition
30:24 RSVD R 7b'0000000 Reserved
23 SMS R/WC 1'b0 Sleep Mode Status (Flag & Not an interrupt) Only sets when sleep mode is entered by a WKERR or TSD fault
22 UVSUP R/WC 1'b0 Under Voltage VSUP and UVCCFLTR
21 RSVD R 1'b0 Reserved
20 PWRON R/WC/U 1'b1 Power ON
19 TSD R/WC 1'b0 Thermal Shutdown
18 RSVD R 1'b0 Reserved
17 RSVD R 1'b0 Reserved
16 ECCERR R/WC 1'b0 Uncorrectable ECC error detected
15 CANINT R/WC 1'b0 Can Bus Wake Up Interrupt
14 LWU R/WC 1'b0 Local Wake Up
13 WKERR R/WC 1'b0 Wake Error
12 RSVD R 1'b0 Reserved
11 RSVD R 1'b0 Reserved
10 CANSLNT R/WC 1'b0 CAN Silent
9 RSVD R 1'b0 Reserved
8 CANDOM R/WC 1'b0 CAN Stuck Dominant
7 GLOBALERR R 1'b0 Global Error (Any Fault)
6 WKRQ R 1'b0 Wake Request
5 CANERR R 1'b0 CAN Error
4 RSVD R 1'b0 RSVD
3 SPIERR R 1'b0 SPI Error
2 RSVD R 1'b0 Reserved
1 M_CAN_INT R 1'b0 M_CAN global INT
0 VTWD R 1'b0 Global Voltage, Temp or WDTO

GLOBALERR: Logical OR of all faults in registers 0x0820-0824.

WKRQ: Logical OR of CANINT, LWU and WKERR.

CANBUSNOM is not an interrupt but a flag. In normal mode after the first dominant-recessive transition it will set. It will reset to 0 when entering Standby or Sleep modes or when a bus fault condition takes place in normal mode.

CANERR: Logical OR of CANSLNT and CANDOM faults.

SPIERR: Will be set if any of the SPI status register 16'h000C[30:16] is set.

  • In the event of a SPI underflow, the error is not detected/alerted until the start of the next SPI transaction.
  • 16'h0010[30:16] are the mask for these errors

VTWD: Logical or of UVCCFLTR, UVSUP, TSD and ECCERR.

CANINT: Indicates a WUP has occurred; Once a CANINT flag is set, LWU events will be ignored. Flag can be cleared by changing to Normal or Sleep modes.

LWU: Indicates a local wake event, from toggling the WAKE pin, has occurred. Once a LWU flag is set, CANINT events will be ignored. Flag can be cleared by changing to Normal or Sleep modes.

WKERR: If the device receives a wake up request and does not transition to Normal mode or clear the PWRON or Wake flag before tINACTIVE, the device will transition to Sleep Mode. After the wake event, a Wake Error (WKERR) will be reported and the SMS flag will be set to 1.

CANTO: CAN Timeout: flag indicates a CAN bus timeout event while in Standby mode with frame detection enabled. If there is no activity on the CAN bus for more than tSILENCE while in Standby mode with frame detect enabled, this flag is set.

NOTE

PWRON Flag is cleared by either writing a 1 or by going to sleep mode or normal mode from standby mode.