SLLSEZ4A August 2019 – November 2019 TCAN4551-Q1
PRODUCTION DATA.
The TCAN4551-Q1 includes a test mode that has four configurations. Two are enabled by the SPI interface using the configuration register by setting register bit 16'h0800[21] = 1. In this mode the transceiver TXD_INT_PHY or CAN core RXD_INT_CAN can be mapped to the GPO1 pin and RXD_INT_PHY or TXD_INT_CAN can be mapped to the GPO2 pin. EN_INT pin is mapped to the nINT pin, seeFigure 27 and Figure 28. This is accomplished by setting register 16'h0800[0] to 0 for transceiver testing or 1 for M_CAN core testing. This mapping is only valid when in test mode. There are two M_CAN core specific test modes entered using SPI but written to the M_CAN core registers directly, see Figure 29 and Figure 30.