SPRS969G August   2016  – November 2019 TDA2EG-17

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  CSI2
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  UART
      10. 4.3.10 McSPI
      11. 4.3.11 QSPI
      12. 4.3.12 McASP
      13. 4.3.13 USB
      14. 4.3.14 PCIe
      15. 4.3.15 DCAN
      16. 4.3.16 GMAC_SW
      17. 4.3.17 eMMC/SD/SDIO
      18. 4.3.18 GPIO
      19. 4.3.19 PWM
      20. 4.3.20 Emulation and Debug Subsystem
      21. 4.3.21 System and Miscellaneous
        1. 4.3.21.1 Sysboot
        2. 4.3.21.2 Power, Reset, and Clock Management (PRCM)
        3. 4.3.21.3 System Direct Memory Access (SDMA)
        4. 4.3.21.4 Interrupt Controllers (INTC)
      22. 4.3.22 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power on Hour (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS CSI2 DC Electrical Characteristics
      6. Table 5-11 Dual Voltage SDIO1833 DC Electrical Characteristics
      7. Table 5-12 Dual Voltage LVCMOS DC Electrical Characteristics
      8. 5.7.1      USBPHY DC Electrical Characteristics
      9. 5.7.2      HDMIPHY DC Electrical Characteristics
      10. 5.7.3      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-13 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics for CBD Package
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8 V and 3.3 V Signal Transition Levels
          2. 5.10.1.1.2 1.8 V and 3.3 V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RC On-die Oscillator Clock
        2. 5.10.4.2 Output Clocks
        3. 5.10.4.3 DPLLs, DLLs
          1. 5.10.4.3.1 DPLL Characteristics
          2. 5.10.4.3.2 DLL Characteristics
          3. 5.10.4.3.3 DPLL and DLL Noise Isolation
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  CSI2
          1. 5.10.6.6.1 CSI-2 MIPI D-PHY
        7. 5.10.6.7  EMIF
        8. 5.10.6.8  GPMC
          1. 5.10.6.8.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.8.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.8.3 GPMC/NAND Flash Interface Asynchronous Timing
        9. 5.10.6.9  Timers
        10. 5.10.6.10 I2C
          1. Table 5-55 Timing Requirements for I2C Input Timings
          2. Table 5-56 Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)
          3. Table 5-57 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        11. 5.10.6.11 UART
          1. Table 5-58 Timing Requirements for UART
          2. Table 5-59 Switching Characteristics Over Recommended Operating Conditions for UART
        12. 5.10.6.12 McSPI
        13. 5.10.6.13 QSPI
        14. 5.10.6.14 McASP
          1. Table 5-66 Timing Requirements for McASP1
          2. Table 5-67 Timing Requirements for McASP2
          3. Table 5-68 Timing Requirements for McASP3/4/5/6/7/8
        15. 5.10.6.15 USB
          1. 5.10.6.15.1 USB1 DRD PHY
          2. 5.10.6.15.2 USB2 PHY
        16. 5.10.6.16 USB3 DRD ULPI—SDR—Slave Mode—12-pin Mode
        17. 5.10.6.17 PCIe3
        18. 5.10.6.18 DCAN
          1. Table 5-86 Timing Requirements for DCANx Receive
          2. Table 5-87 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
        19. 5.10.6.19 GMAC_SW
          1. 5.10.6.19.1 GMAC MII Timings
            1. Table 5-88 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-89 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-90 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-91 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.19.2 GMAC MDIO Interface Timings
          3. 5.10.6.19.3 GMAC RMII Timings
            1. Table 5-96 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-97 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-98 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-99 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.19.4 GMAC RGMII Timings
            1. Table 5-103 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-104 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-105 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-106 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        20. 5.10.6.20 eMMC/SD/SDIO
          1. 5.10.6.20.1 MMC1—SD Card Interface
            1. 5.10.6.20.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.20.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.20.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.20.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.20.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.20.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.20.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.20.2 MMC2 — eMMC
            1. 5.10.6.20.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.20.2.2 High-speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.20.2.3 High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
            4. 5.10.6.20.2.4 High-speed JC64 DDR, 8-bit data
              1. Table 5-131 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
          3. 5.10.6.20.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.20.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.20.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.20.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.20.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.20.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        21. 5.10.6.21 GPIO
        22. 5.10.6.22 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-153 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-154 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-155 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-156 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 Trace Port Interface Unit (TPIU)
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  IVA
    6. 6.6  IPU
    7. 6.7  GPU
    8. 6.8  BB2D
    9. 6.9  Memory Subsystem
      1. 6.9.1 EMIF
      2. 6.9.2 GPMC
      3. 6.9.3 ELM
      4. 6.9.4 OCMC
    10. 6.10 Interprocessor Communication
      1. 6.10.1 MailBox
      2. 6.10.2 Spinlock
    11. 6.11 Interrupt Controller
    12. 6.12 EDMA
    13. 6.13 Peripherals
      1. 6.13.1  VIP
      2. 6.13.2  DSS
      3. 6.13.3  Timers
        1. 6.13.3.1 General-Purpose Timers
        2. 6.13.3.2 32-kHz Synchronized Timer (COUNTER_32K)
        3. 6.13.3.3 Watchdog Timer
      4. 6.13.4  I2C
      5. 6.13.5  UART
        1. 6.13.5.1 UART Features
        2. 6.13.5.2 IrDA Features
        3. 6.13.5.3 CIR Features
      6. 6.13.6  McSPI
      7. 6.13.7  QSPI
      8. 6.13.8  McASP
      9. 6.13.9  USB
      10. 6.13.10 PCIe
      11. 6.13.11 DCAN
      12. 6.13.12 GMAC_SW
      13. 6.13.13 eMMC/SD/SDIO
      14. 6.13.14 GPIO
      15. 6.13.15 ePWM
      16. 6.13.16 eCAP
      17. 6.13.17 eQEP
    14. 6.14 On-chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 7.5.2.1 Background
        2. 7.5.2.2 USB PHY Layout Guide
          1. 7.5.2.2.1 General Routing and Placement
          2. 7.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 7.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 7.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 7.5.2.2.2.3  Board Stackup
            4. 7.5.2.2.2.4  Cable Connector Socket
            5. 7.5.2.2.2.5  Clock Routings
            6. 7.5.2.2.2.6  Crystals/Oscillator
            7. 7.5.2.2.2.7  DP/DM Trace
            8. 7.5.2.2.2.8  DP/DM Vias
            9. 7.5.2.2.2.9  Image Planes
            10. 7.5.2.2.2.10 Power Regulators
        3. 7.5.2.3 References
      3. 7.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 7.5.3.1 USB 3.0 interface introduction
        2. 7.5.3.2 USB 3.0 General routing rules
      4. 7.5.4 HDMI Board Design and Layout Guidelines
        1. 7.5.4.1 HDMI Interface Schematic
        2. 7.5.4.2 TMDS General Routing Guidelines
        3. 7.5.4.3 TPD5S115
        4. 7.5.4.4 HDMI ESD Protection Device (Required)
        5. 7.5.4.5 PCB Stackup Specifications
        6. 7.5.4.6 Grounding
      5. 7.5.5 PCIe Board Design and Layout Guidelines
        1. 7.5.5.1 PCIe Connections and Interface Compliance
          1. 7.5.5.1.1 Coupling Capacitors
          2. 7.5.5.1.2 Polarity Inversion
        2. 7.5.5.2 Non-standard PCIe connections
          1. 7.5.5.2.1 PCB Stackup Specifications
          2. 7.5.5.2.2 Routing Specifications
            1. 7.5.5.2.2.1 Impedance
            2. 7.5.5.2.2.2 Differential Coupling
            3. 7.5.5.2.2.3 Pair Length Matching
        3. 7.5.5.3 LJCB_REFN/P Connections
      6. 7.5.6 CSI2 Board Design and Routing Guidelines
        1. 7.5.6.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          1. 7.5.6.1.1 General Guidelines
          2. 7.5.6.1.2 Length Mismatch Guidelines
            1. 7.5.6.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          3. 7.5.6.1.3 Frequency-domain Specification Guidelines
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7 DDR3 Board Design and Layout Guidelines
      1. 7.7.1 DDR3 General Board Layout Guidelines
      2. 7.7.2 DDR3 Board Design and Layout Guidelines
        1. 7.7.2.1  Board Designs
        2. 7.7.2.2  DDR3 EMIF
        3. 7.7.2.3  DDR3 Device Combinations
        4. 7.7.2.4  DDR3 Interface Schematic
          1. 7.7.2.4.1 32-Bit DDR3 Interface
          2. 7.7.2.4.2 16-Bit DDR3 Interface
        5. 7.7.2.5  Compatible JEDEC DDR3 Devices
        6. 7.7.2.6  PCB Stackup
        7. 7.7.2.7  Placement
        8. 7.7.2.8  DDR3 Keepout Region
        9. 7.7.2.9  Bulk Bypass Capacitors
        10. 7.7.2.10 High-Speed Bypass Capacitors
          1. 7.7.2.10.1 Return Current Bypass Capacitors
        11. 7.7.2.11 Net Classes
        12. 7.7.2.12 DDR3 Signal Termination
        13. 7.7.2.13 VREF_DDR Routing
        14. 7.7.2.14 VTT
        15. 7.7.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.7.2.15.1 Four DDR3 Devices
            1. 7.7.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.7.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.7.2.15.2 Two DDR3 Devices
            1. 7.7.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.7.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.7.2.15.3 One DDR3 Device
            1. 7.7.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.7.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.7.2.16 Data Topologies and Routing Definition
          1. 7.7.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.7.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.7.2.17 Routing Specification
          1. 7.7.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.7.2.17.2 DQS and DQ Routing Specification
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • CBD|538
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.3.1 VIP

NOTE

For more information, see the Video Input Port (VIP) section of the device TRM.

Table 4-2 VIP Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
Video Input 1
vin1a_clk0 Video Input 1 Port A Clock input.Input clock for 8-bit 16-bit or 24-bit Port A video capture. Input data is sampled on the CLK0 edge. I G3, J24, Y5
vin1a_d0 Video Input 1 Port A Data input I AA1, B23, F1, J25
vin1a_d1 Video Input 1 Port A Data input I B22, E2, Y3
vin1a_d2 Video Input 1 Port A Data input I A23, E1, W2
vin1a_d3 Video Input 1 Port A Data input I A22, AA3, C1
vin1a_d4 Video Input 1 Port A Data input I AA2, B21, D1
vin1a_d5 Video Input 1 Port A Data input I A21, D2, Y4
vin1a_d6 Video Input 1 Port A Data input I B1, D19, Y1
vin1a_d7 Video Input 1 Port A Data input I B2, E19, Y2
vin1a_d8 Video Input 1 Port A Data input I C2, F16
vin1a_d9 Video Input 1 Port A Data input I D3, E16
vin1a_d10 Video Input 1 Port A Data input I A2, E17
vin1a_d11 Video Input 1 Port A Data input I A19, B3
vin1a_d12 Video Input 1 Port A Data input I B18, C3
vin1a_d13 Video Input 1 Port A Data input I B16, C4
vin1a_d14 Video Input 1 Port A Data input I A3, B17
vin1a_d15 Video Input 1 Port A Data input I A18, B4
vin1a_d16 Video Input 1 Port A Data input I M1
vin1a_d17 Video Input 1 Port A Data input I M2
vin1a_d18 Video Input 1 Port A Data input I L2
vin1a_d19 Video Input 1 Port A Data input I L1
vin1a_d20 Video Input 1 Port A Data input I K3
vin1a_d21 Video Input 1 Port A Data input I K2
vin1a_d22 Video Input 1 Port A Data input I J1
vin1a_d23 Video Input 1 Port A Data input I K1
vin1a_de0 Video Input 1 Port A Field ID input I C17, J2, Y6
vin1a_fld0 Video Input 1 Port A Field ID input I C16, L3
vin1a_hsync0 Video Input 1 Port A Horizontal Sync input I AA4, B14, K4
vin1a_vsync0 Video Input 1 Port A Vertical Sync input I AB1, D14, H1
vin1b_clk1 Video Input 1 Port B Clock input I J2, L5
vin1b_d0 Video Input 1 Port B Data input I L6, M1
vin1b_d1 Video Input 1 Port B Data input I M2, N5
vin1b_d2 Video Input 1 Port B Data input I L2, N6
vin1b_d3 Video Input 1 Port B Data input I L1, T4
vin1b_d4 Video Input 1 Port B Data input I K3, T5
vin1b_d5 Video Input 1 Port B Data input I K2, N2
vin1b_d6 Video Input 1 Port B Data input I J1, P2
vin1b_d7 Video Input 1 Port B Data input I K1, N1
vin1b_de1 Video Input 1 Port B Field ID input I L3, P4
vin1b_fld1 Video Input 1 Port B Field ID input I G1, N4
vin1b_hsync1 Video Input 1 Port B Horizontal Sync input I K4, P3
vin1b_vsync1 Video Input 1 Port B Vertical Sync input I H1, R2
Video Input 2
vin2a_clk0 Video Input 2 Port A Clock input. I D8, L5
vin2a_d0 Video Input 2 Port A Data input I C8, L6
vin2a_d1 Video Input 2 Port A Data input I B9, N5
vin2a_d2 Video Input 2 Port A Data input I A7, N6
vin2a_d3 Video Input 2 Port A Data input I A9, T4
vin2a_d4 Video Input 2 Port A Data input I A8, T5
vin2a_d5 Video Input 2 Port A Data input I A11, N2
vin2a_d6 Video Input 2 Port A Data input I F10, P2
vin2a_d7 Video Input 2 Port A Data input I A10, N1
vin2a_d8 Video Input 2 Port A Data input I B10, P1
vin2a_d9 Video Input 2 Port A Data input I E10, N3
vin2a_d10 Video Input 2 Port A Data input I D10, R1
vin2a_d11 Video Input 2 Port A Data input I C10, P5
vin2a_d12 Video Input 2 Port A Data input I B11
vin2a_d13 Video Input 2 Port A Data input I D11
vin2a_d14 Video Input 2 Port A Data input I C11
vin2a_d15 Video Input 2 Port A Data input I B12
vin2a_d16 Video Input 2 Port A Data input I A12
vin2a_d17 Video Input 2 Port A Data input I A13
vin2a_d18 Video Input 2 Port A Data input I E11
vin2a_d19 Video Input 2 Port A Data input I F11
vin2a_d20 Video Input 2 Port A Data input I B13
vin2a_d21 Video Input 2 Port A Data input I E13
vin2a_d22 Video Input 2 Port A Data input I C13
vin2a_d23 Video Input 2 Port A Data input I D13
vin2a_de0 Video Input 2 Port A Field ID input I B7, P4
vin2a_fld0 Video Input 2 Port A Field ID input I B7, C7, N4
vin2a_hsync0 Video Input 2 Port A Horizontal Sync input I E8, P3
vin2a_vsync0 Video Input 2 Port A Vertical Sync input I B8, R2
vin2b_clk1 Video Input 2 Port B Clock input I AB1, C7, L4, H6
vin2b_d0 Video Input 2 Port B Data input I AA1, D13, A4
vin2b_d1 Video Input 2 Port B Data input I C13, Y3, E7
vin2b_d2 Video Input 2 Port B Data input I E13, W2, D6
vin2b_d3 Video Input 2 Port B Data input I AA3, B13, C5
vin2b_d4 Video Input 2 Port B Data input I AA2, F11, B5
vin2b_d5 Video Input 2 Port B Data input I E11, Y4, D7
vin2b_d6 Video Input 2 Port B Data input I A13, Y1, C6
vin2b_d7 Video Input 2 Port B Data input I A12, Y2, A5
vin2b_de1 Video Input 2 Port B Field ID input I AA4, B7, H2
vin2b_fld1 Video Input 2 Port B Field ID input I B7, H6
vin2b_hsync1 Video Input 2 Port B Horizontal Sync input I E8, Y5, B6
vin2b_vsync1 Video Input 2 Port B Vertical Sync input I B8, Y6, A6