SPRS951 Data sheet

SPRS951F December 2015 – May 2019 TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2SA , TDA2SG , TDA2SX

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

ABC|760

Thermal pad, mechanical data (Package|Pins)

Orderable Information

sprs951f_oa

3 Device Comparison

Table 3-1 shows a comparison between devices, highlighting the differences.

Table 3-1 Device Comparison^⁽³⁾

FEATURES			DEVICE
			TDA2Sxx			TDA2Hxx			TDA2LFx
			TDA2SXx	TDA2SGx	TDA2SAx	TDA2HGx	TDA2HVx	TDA2HFx	TDA2LFx
Features
CTRL_WKUP_STD_FUSE_DIE_ID_2[31:24] Base PN register bitfield value ^{⁽²⁾⁽³⁾}			51 (0x33)	50 (0x32)	45 (0x2D)	42 (0x2A)	38 (0x26)	41 (0x29)	25 (0x19)
Processors/Accelerators
Speed Grades			T	R	R	R, D		T	T, F
Dual Arm Cortex-A15 Microprocessor Subsystem (MPU)		MPU core 0	Yes		Yes	Yes		Yes	Yes
Dual Arm Cortex-A15 Microprocessor Subsystem (MPU)		MPU core 1	Yes	No	No	No		Yes	Yes
C66x VLIW DSP		DSP1	Yes		Yes	Yes		Yes	No
C66x VLIW DSP		DSP2	Yes		Yes	Yes		Yes	No
BitBLT 2D Hardware Acceleration Engine (BB2D)		BB2D	Yes		No	Yes	No	Yes	No
Display Subsystem		VOUT1	Yes		Yes	Yes		Yes	No
		VOUT2	Yes		Yes	Yes		Yes	No
		VOUT3	Yes		Yes	Yes		Yes	No
		HDMI	Yes		Yes	Yes		Yes	No
Embedded Vision Engine (EVE)		EVE1	Yes		Yes	Yes		Yes	No
		EVE2	Yes		Yes	Yes		Yes	No
		EVE3	Yes		Yes	No		No	No
		EVE4	Yes		Yes	No		No	No
Dual Arm Cortex-M4 Image Processing Unit (IPU)		IPU1	Yes		Yes	Yes		Yes	Yes
Dual Arm Cortex-M4 Image Processing Unit (IPU)		IPU2	Yes		Yes	Yes		Yes	Yes
Image Video Accelerator		IVA	Yes		Yes	Yes	Yes	Yes	No
SGX544 Dual-Core 3D Graphics Processing Unit		GPU	Yes		No	Yes	No	Yes	No
Video Input Port (VIP)	VIP1	vin1a	Yes		Yes	Yes		Yes	No
		vin1b	Yes		Yes	Yes		Yes	No
		vin2a	Yes		Yes	Yes		Yes	No
		vin2b	Yes		Yes	Yes		Yes	No
	VIP2	vin3a	Yes		Yes	Yes		Yes	No
		vin3b	Yes		Yes	Yes		Yes	No
		vin4a	Yes		Yes	Yes		Yes	No
		vin4b	Yes		Yes	Yes		Yes	No
	VIP3	vin5a	Yes		Yes	Yes		Yes	No
	VIP3	vin6a	Yes		Yes	Yes		Yes	No
Video Processing Engine		VPE	Yes		Yes	Yes		Yes	No
Program/Data Storage
On-Chip Shared Memory (RAM)		OCMC_RAM1	512KB		512KB	512KB		512KB	512KB
		OCMC_RAM2	1MB		1MB	1MB		1MB	1MB
		OCMC_RAM3	1MB		1MB	1MB		1MB	1MB
General-Purpose Memory Controller		GPMC	Yes		Yes	Yes		Yes	Yes
DDR2/DDR3 Memory Controller ^⁽¹⁾		EMIF1 (with SECDEC)	up to 2GB		up to 2GB	up to 2GB		up to 2GB	up to 2GB
DDR2/DDR3 Memory Controller ^⁽¹⁾		EMIF2	up to 2GB		up to 2GB	up to 2GB		up to 2GB	up to 2GB
Dynamic Memory Manager		DMM	Yes		Yes	Yes		Yes	Yes
Peripherals
Dual Controller Area Network Interface (DCAN)		DCAN1	Yes		Yes	Yes		Yes	Yes
Dual Controller Area Network Interface (DCAN)		DCAN2	Yes		Yes	Yes		Yes	Yes
Enhanced DMA (EDMA)		EDMA	Yes		Yes	Yes		Yes	Yes
System DMA		SDMA	Yes		Yes	Yes		Yes	Yes
Ethernet Subsystem (Ethernet SS)		GMAC_SW[0]	Yes		Yes	Yes		Yes	Yes
		GMAC_SW[1]	Yes		Yes	Yes		Yes	Yes
		Ethernet switch	Yes		Yes	Yes		Yes	Yes
General-Purpose I/O		GPIO	up to 247		up to 247	up to 247		up to 247	up to 247
Inter-Integrated Circuit Interface		I2C	5		5	5		5	5
System Mailbox Module		MAILBOX	13		13	13		13	13
Multichannel Audio Serial Port (McASP)		McASP1	16 serializers		16 serializers	16 serializers		16 serializers	16 serializers
		McASP2	16 serializers		16 serializers	16 serializers		16 serializers	16 serializers
		McASP3	4 serializers		4 serializers	4 serializers		4 serializers	4 serializers
		McASP4	4 serializers		4 serializers	4 serializers		4 serializers	4 serializers
		McASP5	4 serializers		4 serializers	4 serializers		4 serializers	4 serializers
		McASP6	4 serializers		4 serializers	4 serializers		4 serializers	4 serializers
		McASP7	4 serializers		4 serializers	4 serializers		4 serializers	4 serializers
		McASP8	4 serializers		4 serializers	4 serializers		4 serializers	4 serializers
MultiMedia Card/Secure Digital/Secure Digital Input Output Interface (MMC/SD/SDIO)		MMC1	1x UHSI 4b		1x UHSI 4b	1x UHSI 4b		1x UHSI 4b	1x UHSI 4b
		MMC2	1x eMMC™ 8b		1x eMMC™ 8b	1x eMMC 8b		1x eMMC 8b	1x eMMC 8b
		MMC3	1x SDIO 8b		1x SDIO 8b	1x SDIO 8b		1x SDIO 8b	1x SDIO 8b
		MMC4	1x SDIO 4b		1x SDIO 4b	1x SDIO 4b		1x SDIO 4b	1x SDIO 4b
PCI Express 3.0 Port with Integrated PHY		PCIe_SS1	Yes		Yes	Yes		Yes	Yes
PCI Express 3.0 Port with Integrated PHY		PCIe_SS2	Yes		Yes	Yes		Yes	Yes
SATA Gen2 Interface		SATA	Yes		Yes	Yes		Yes	Yes
Real-Time Clock Subsystem		RTCSS	Yes		Yes	Yes		Yes	Yes
Multichannel Serial Peripheral Interface		McSPI	4		4	4		4	4
Quad SPI		QSPI	Yes		Yes	Yes		Yes	Yes
Spinlock Module		SPINLOCK	Yes		Yes	Yes		Yes	Yes
Timers, General-Purpose		TIMER	16		16	16		16	16
Timer, Watchdog		WATCHDOG TIMER	Yes		Yes	Yes		Yes	Yes
Pulse-Width Modulation Subsystem (PWMSS)		PWMSS1	Yes		Yes	Yes		Yes	Yes
		PWMSS2	Yes		Yes	Yes		Yes	Yes
		PWMSS3	Yes		Yes	Yes		Yes	Yes
Universal Asynchronous Receiver/Transmitter		UART	10		10	10		10	10
Universal Serial Bus (USB3.0)		USB1 (SuperSpeed, Dual-Role-Device [DRD])	Yes		Yes	Yes		Yes	Yes
Universal Serial Bus (USB2.0)		USB2 (HighSpeed, Dual-Role-Device [DRD], with embedded HS PHY	Yes		Yes	Yes		Yes	Yes
		USB3 (HighSpeed, OTG2.0, with ULPI)	Yes		Yes	Yes		Yes	Yes
		USB4 (HighSpeed, OTG2.0, with ULPI)	Yes		Yes	Yes		Yes	Yes

In the Unified L3 memory map, there is maximum of 2GB of SDRAM space which is available to all L3 initiators including MPU (MPU, GPU, DSP, IVA, DMA, etc). Typically this space is interleaved across both EMIFs to optimize memory performance. If a system populates > 2GB of physical memory, that additional addressable space can be accessed only by the MPU via the Arm V7 Large Physical Address Extensions (LPAE).
For more details about the CTRL_WKUP_STD_FUSE_DIE_ID_2 register and Base PN bitfield, see the TDA2x SoC for Advanced Driver Assistance Systems (ADAS) Silicon Revision 2.0, 1.x.
X5777x is the base part number for the superset device. Software should constrain the features used to match the intended production device. The Base PN register bitfield value is 0x3F.