SPRS996 Data sheet

SPRS996F March 2017 – February 2019 TDA2P-ACD

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

ACD|784
- MPBGAN2A

Thermal pad, mechanical data (Package|Pins)

Orderable Information

sprs996f_oa

4.3.5 EMIF

NOTE

For more information, see the Memory Subsystem / EMIF Controller section of the Device TRM.

Table 4-6 EMIF Signal Descriptions

SIGNAL NAME	DESCRIPTION	TYPE	BALL
EMIF Channel 1
ddr1_casn	EMIF1 Column Address Strobe	O	AG19
ddr1_ck	EMIF1 Clock	O	AG24
ddr1_cke	EMIF1 Clock Enable	O	AH23
ddr1_dqm_ecc	EMIF1 ECC Data Mask	O	T27
ddr1_dqsn_ecc	EMIF1 ECC Complementary Data Strobe	IO	U28
ddr1_dqs_ecc	EMIF1 ECC Data Strobe input/output. This signal is output to the EMIF1 memory when writing and input when reading.	IO	U27
ddr1_nck	EMIF1 Negative Clock	O	AH24
ddr1_rasn	EMIF1 Row Address Strobe	O	AH20
ddr1_rst	EMIF1 Reset output (DDR3-SDRAM only)	O	AF23
ddr1_wen	EMIF1 Write Enable	O	AG22
ddr1_a0	EMIF1 Address Bus	O	AE22
ddr1_a1	EMIF1 Address Bus	O	AD20
ddr1_a2	EMIF1 Address Bus	O	AE21
ddr1_a3	EMIF1 Address Bus	O	AD22
ddr1_a4	EMIF1 Address Bus	O	AE23
ddr1_a5	EMIF1 Address Bus	O	AH22
ddr1_a6	EMIF1 Address Bus	O	AD24
ddr1_a7	EMIF1 Address Bus	O	AC22
ddr1_a8	EMIF1 Address Bus	O	AG23
ddr1_a9	EMIF1 Address Bus	O	AF24
ddr1_a10	EMIF1 Address Bus	O	AD21
ddr1_a11	EMIF1 Address Bus	O	AE24
ddr1_a12	EMIF1 Address Bus	O	AG21
ddr1_a13	EMIF1 Address Bus	O	AF21
ddr1_a14	EMIF1 Address Bus	O	AC23
ddr1_a15	EMIF1 Address Bus	O	AG20
ddr1_ba0	EMIF1 Bank Address	O	AE20
ddr1_ba1	EMIF1 Bank Address	O	AC21
ddr1_ba2	EMIF1 Bank Address	O	AH21
ddr1_csn0	EMIF1 Chip Select 0	O	AD23
ddr1_d0	EMIF1 Data Bus	IO	AE26
ddr1_d1	EMIF1 Data Bus	IO	AE27
ddr1_d2	EMIF1 Data Bus	IO	AF28
ddr1_d3	EMIF1 Data Bus	IO	AH26
ddr1_d4	EMIF1 Data Bus	IO	AF25
ddr1_d5	EMIF1 Data Bus	IO	AG27
ddr1_d6	EMIF1 Data Bus	IO	AF27
ddr1_d7	EMIF1 Data Bus	IO	AF26
ddr1_d8	EMIF1 Data Bus	IO	AB24
ddr1_d9	EMIF1 Data Bus	IO	AD27
ddr1_d10	EMIF1 Data Bus	IO	AE28
ddr1_d11	EMIF1 Data Bus	IO	AD28
ddr1_d12	EMIF1 Data Bus	IO	AD26
ddr1_d13	EMIF1 Data Bus	IO	AE25
ddr1_d14	EMIF1 Data Bus	IO	AD25
ddr1_d15	EMIF1 Data Bus	IO	AC26
ddr1_d16	EMIF1 Data Bus	IO	AA25
ddr1_d17	EMIF1 Data Bus	IO	AB25
ddr1_d18	EMIF1 Data Bus	IO	AA26
ddr1_d19	EMIF1 Data Bus	IO	AA28
ddr1_d20	EMIF1 Data Bus	IO	AA27
ddr1_d21	EMIF1 Data Bus	IO	AA24
ddr1_d22	EMIF1 Data Bus	IO	AC25
ddr1_d23	EMIF1 Data Bus	IO	Y26
ddr1_d24	EMIF1 Data Bus	IO	W26
ddr1_d25	EMIF1 Data Bus	IO	AB23
ddr1_d26	EMIF1 Data Bus	IO	V24
ddr1_d27	EMIF1 Data Bus	IO	Y24
ddr1_d28	EMIF1 Data Bus	IO	W25
ddr1_d29	EMIF1 Data Bus	IO	Y25
ddr1_d30	EMIF1 Data Bus	IO	W24
ddr1_d31	EMIF1 Data Bus	IO	Y28
ddr1_dqm0	EMIF1 Data Mask	O	AG26
ddr1_dqm1	EMIF1 Data Mask	O	AC24
ddr1_dqm2	EMIF1 Data Mask	O	AB26
ddr1_dqm3	EMIF1 Data Mask	O	Y27
ddr1_dqs0	Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading.	IO	AH25
ddr1_dqs1	Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading.	IO	AC27
ddr1_dqs2	Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading.	IO	AB27
ddr1_dqs3	Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading.	IO	W28
ddr1_dqsn0	Data strobe 0 invert	IO	AG25
ddr1_dqsn1	Data strobe 1 invert	IO	AC28
ddr1_dqsn2	Data strobe 2 invert	IO	AB28
ddr1_dqsn3	Data strobe 3 invert	IO	W27
ddr1_ecc_d0	EMIF1 ECC Data Bus	IO	U25
ddr1_ecc_d1	EMIF1 ECC Data Bus	IO	U26
ddr1_ecc_d2	EMIF1 ECC Data Bus	IO	V25
ddr1_ecc_d3	EMIF1 ECC Data Bus	IO	V26
ddr1_ecc_d4	EMIF1 ECC Data Bus	IO	V27
ddr1_ecc_d5	EMIF1 ECC Data Bus	IO	T28
ddr1_ecc_d6	EMIF1 ECC Data Bus	IO	T26
ddr1_ecc_d7	EMIF1 ECC Data Bus	IO	V28
ddr1_odt0	EMIF1 On-Die Termination for Chip Select 0	O	AF22
EMIF Channel 2
ddr2_casn	EMIF2 Column Address Strobe	O	T25
ddr2_ck	EMIF2 Clock	O	R28
ddr2_cke	EMIF2 Clock Enable	O	R25
ddr2_nck	EMIF2 Negative Clock	O	R27
ddr2_rasn	EMIF2 Row Address Strobe	O	R26
ddr2_rst	EMIF2 Reset output (DDR3-SDRAM only)	O	N25
ddr2_wen	EMIF2 Write Enable	O	T24
ddr2_a0	EMIF2 Address Bus	O	P25
ddr2_a1	EMIF2 Address Bus	O	P26
ddr2_a2	EMIF2 Address Bus	O	P28
ddr2_a3	EMIF2 Address Bus	O	P27
ddr2_a4	EMIF2 Address Bus	O	P24
ddr2_a5	EMIF2 Address Bus	O	P23
ddr2_a6	EMIF2 Address Bus	O	N26
ddr2_a7	EMIF2 Address Bus	O	M25
ddr2_a8	EMIF2 Address Bus	O	N28
ddr2_a9	EMIF2 Address Bus	O	M27
ddr2_a10	EMIF2 Address Bus	O	L25
ddr2_a11	EMIF2 Address Bus	O	N27
ddr2_a12	EMIF2 Address Bus	O	M28
ddr2_a13	EMIF2 Address Bus	O	R24
ddr2_a14	EMIF2 Address Bus	O	N24
ddr2_a15	EMIF2 Address Bus	O	R23
ddr2_ba0	EMIF2 Bank Address	O	L24
ddr2_ba1	EMIF2 Bank Address	O	U24
ddr2_ba2	EMIF2 Bank Address	O	M24
ddr2_csn0	EMIF2 Chip Select 0	O	M26
ddr2_d0	EMIF2 Data Bus	IO	C28
ddr2_d1	EMIF2 Data Bus	IO	A26
ddr2_d2	EMIF2 Data Bus	IO	E24
ddr2_d3	EMIF2 Data Bus	IO	D25
ddr2_d4	EMIF2 Data Bus	IO	D26
ddr2_d5	EMIF2 Data Bus	IO	B27
ddr2_d6	EMIF2 Data Bus	IO	B26
ddr2_d7	EMIF2 Data Bus	IO	C26
ddr2_d8	EMIF2 Data Bus	IO	F26
ddr2_d9	EMIF2 Data Bus	IO	E25
ddr2_d10	EMIF2 Data Bus	IO	E26
ddr2_d11	EMIF2 Data Bus	IO	G27
ddr2_d12	EMIF2 Data Bus	IO	E28
ddr2_d13	EMIF2 Data Bus	IO	G26
ddr2_d14	EMIF2 Data Bus	IO	G28
ddr2_d15	EMIF2 Data Bus	IO	F25
ddr2_d16	EMIF2 Data Bus	IO	G25
ddr2_d17	EMIF2 Data Bus	IO	G24
ddr2_d18	EMIF2 Data Bus	IO	F23
ddr2_d19	EMIF2 Data Bus	IO	F24
ddr2_d20	EMIF2 Data Bus	IO	H28
ddr2_d21	EMIF2 Data Bus	IO	H25
ddr2_d22	EMIF2 Data Bus	IO	H27
ddr2_d23	EMIF2 Data Bus	IO	H26
ddr2_d24	EMIF2 Data Bus	IO	K27
ddr2_d25	EMIF2 Data Bus	IO	K26
ddr2_d26	EMIF2 Data Bus	IO	J25
ddr2_d27	EMIF2 Data Bus	IO	K28
ddr2_d28	EMIF2 Data Bus	IO	H24
ddr2_d29	EMIF2 Data Bus	IO	J24
ddr2_d30	EMIF2 Data Bus	IO	K24
ddr2_d31	EMIF2 Data Bus	IO	L26
ddr2_dqm0	EMIF2 Data Mask	O	C27
ddr2_dqm1	EMIF2 Data Mask	O	E27
ddr2_dqm2	EMIF2 Data Mask	O	G23
ddr2_dqm3	EMIF2 Data Mask	O	J26
ddr2_dqs0	Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the EMIF2 memory when writing and input when reading.	IO	D28
ddr2_dqs1	Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the EMIF2 memory when writing and input when reading.	IO	F27
ddr2_dqs2	Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the EMIF2 memory when writing and input when reading.	IO	J27
ddr2_dqs3	Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the EMIF2 memory when writing and input when reading.	IO	L28
ddr2_dqsn0	Data strobe 0 invert	IO	D27
ddr2_dqsn1	Data strobe 1 invert	IO	F28
ddr2_dqsn2	Data strobe 2 invert	IO	J28
ddr2_dqsn3	Data strobe 3 invert	IO	L27
ddr2_odt0	EMIF2 On-Die Termination for Chip Select 0	O	K25

NOTE

DDR SDRAM Channel 2 is not supported by Vision High Surround, Vision High and Vision Mid devices.

For more details on the device differentiation, refer to Table 3-1, Device Comparison.

NOTE

The index numbers 1 and 2 which is part of the EMIF1 and EMIF2 signal prefixes (ddr1_* and ddr2_*) listed in Table 4-6, DDR2/DDR3/DDR3L SDRAM Signal Descriptions, column "SIGNAL NAME" not to be confused with DDR1 and DDR2 types of SDRAM memories.