SPRS964 Data sheet

SPRS964H June 2016 – February 2020 TDA3LA , TDA3LX , TDA3MA , TDA3MD , TDA3MV

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

ABF|367

Thermal pad, mechanical data (Package|Pins)

Orderable Information

sprs964h_oa

7.14 Quad Serial Peripheral Interface (QSPI)

The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to external SPI devices. This module has a memory mapped register interface, which provides a direct interface for accessing data from external SPI devices and thus simplifying software requirements. It works as a master only. There is one QSPI module in the device and it is primary intended for fast booting from quad-SPI flash memories.

General SPI features:

Programmable clock divider
Six pin interface (DCLK, CS_N, DOUT, DIN, QDIN1, QDIN2)
4 external chip select signals
Support for 3-, 4- or 6-pin SPI interface
Programmable CS_N to DOUT delay from 0 to 3 DCLKs
Programmable signal polarities
Programmable active clock edge
Software controllable interface allowing for any type of SPI transfer

NOTE

For more information, see the Quad Serial Peripheral Interface section of the Device TRM.

Table 7-23 and Table 7-24 present Timing and Switching Characteristics for Quad SPI Interface.

Table 7-23 Switching Characteristics for QSPI

No	PARAMETER	DESCRIPTION	Mode	MIN	MAX	UNIT
1	t_c(SCLK)	Cycle time, sclk	Default Timing Mode, Clock Mode 0	10.4		ns
1	t_c(SCLK)	Cycle time, sclk	Default Timing Mode, Clock Mode 3	15.625		ns
2	t_w(SCLKL)	Pulse duration, sclk low		Y×P-1 ⁽¹⁾		ns
3	t_w(SCLKH)	Pulse duration, sclk high		Y×P-1 ⁽¹⁾		ns
4	t_d(CS-SCLK)	Delay time, sclk falling edge to cs active edge, CS3:0	Default Timing Mode	-M×P-1 ⁽²⁾⁽³⁾	-M×P+1 ⁽²⁾⁽³⁾	ns
5	t_d(SCLK-CS)	Delay time, sclk falling edge to cs inactive edge, CS3:0	Default Timing Mode	N×P-1 ⁽²⁾⁽³⁾	N×P+1 ⁽²⁾⁽³⁾	ns
6	t_d(SCLK-D1)	Delay time, sclk falling edge to d[0] transition	Default Timing Mode	-1	1	ns
7	t_ena(CS-D1LZ)	Enable time, cs active edge to d[0] driven (lo-z)		-P-3.5	-P+2.5	ns
8	t_dis(CS-D1Z)	Disable time, cs active edge to d[0] tri-stated (hi-z)		-P-2.5	-P+2.0	ns
9	t_d(SCLK-D1)	Delay time, sclk first falling edge to first d[0] transition	PHA=0 Only, Default Timing Mode	-1-P	-1-P	ns

The Y parameter is defined as follows: If DCLK_DIV is 0 or ODD then, Y equals 0.5. If DCLK_DIV is EVEN then, Y equals (DCLK_DIV/2) / (DCLK_DIV+1). For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle distortion. The HSDIVIDER on CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All required details about clock division factor DCLK_DIV can be found in the device-specific Technical Reference Manual.
P = SCLK period.
M=QSPI_SPI_DC_REG.DDx + 1 when Clock Mode 0. M=QSPI_SPI_DC_REG.DDx when Clock Mode 3. N = 2 when Clock Mode 0. N = 3 when Clock Mode 3.

TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA SPRS91v_QSPI_01.gif

Figure 7-30 QSPI Read (Clock Mode 3)

TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA SPRS91v_QSPI_02.gif

Figure 7-31 QSPI Read (Clock Mode 0)

CAUTION

The IO Timings provided in this section are only valid when all QSPI Chip Selects used in a system are configured to use the same Clock Mode (either Clock Mode 0 or Clock Mode 3).

Table 7-24 Timing Requirements for QSPI

No	PARAMETER	DESCRIPTION	MODE	MIN	UNIT
12	t_su(D-RTCLK)	Setup time, d[3:0] valid before falling rtclk edge	Default Timing Mode, Clock Mode 0	2.9	ns
12	t_su(D-SCLK)	Setup time, d[3:0] valid before falling sclk edge	Default Timing Mode, Clock Mode 3	5.7	ns
13	t_h(RTCLK-D)	Hold time, d[3:0] valid after falling rtclk edge	Default Timing Mode, Clock Mode 0	-0.1	ns
13	t_h(SCLK-D)	Hold time, d[3:0] valid after falling sclk edge	Default Timing Mode, Clock Mode 3	0.1	ns
14	t_su(D-SCLK)	Setup time, final d[3:0] bit valid before final falling sclk edge	Default Timing Mode, Clock Mode 3	5.7-P ⁽¹⁾	ns
15	t_h(SCLK-D)	Hold time, final d[3:0] bit valid after final falling sclk edge	Default Timing Mode, Clock Mode 3	0.1+P ⁽¹⁾	ns

P = SCLK period.
Clock Modes 1 and 2 are not supported.
The Device captures data on the falling clock edge in Clock Mode 0 and 3, as opposed to the traditional rising clock edge. Although non-standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that launch data on the falling edge in Clock Modes 0 and 3.

TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA SPRS91v_QSPI_03.gif

Figure 7-32 QSPI Write (Clock Mode 3)

TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA SPRS91v_QSPI_04.gif

Figure 7-33 QSPI Write (Clock Mode 0)

NOTE

To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bit field for each corresponding pad control register.

The pad control registers are presented in Table 4-3 and described in Device TRM, Control Module section.

CAUTION

The IO timings provided in this section are only valid if signals within a single IOSET are used. The IOSETs are defined in Table 7-25.

In Table 7-25 are presented the specific groupings of signals (IOSET) for use with QSPI.

Table 7-25 QSPI IOSETs

SIGNALS	IOSET1		IOSET2		IOSET3		IOSET4
SIGNALS	BALL	MUX	BALL	MUX	BALL	MUX	BALL	MUX
qspi1_sclk	C8	1	C8	1	C8	1	C8	1
qspi1_rtclk	C14	8	B7	1	F13	5	D8	2
qspi1_d0	B9	1	B9	1	B9	1	B9	1
qspi1_d1	F10	1	F10	1	F10	1	F10	1
qspi1_d2	A9	1	A9	1	A9	1	A9	1
qspi1_d3	D10	1	D10	1	D10	1	D10	1
qspi1_cs0	E10	1	E10	1	E10	1	E10	1
qspi1_cs1	F15	5	F15	5	F15	5	F15	5