SPRS964 Data sheet

SPRS964H June 2016 – February 2020 TDA3LA , TDA3LX , TDA3MA , TDA3MD , TDA3MV

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

ABF|367

Thermal pad, mechanical data (Package|Pins)

Orderable Information

sprs964h_oa

6.2.1 DPLL Characteristics

The DPLL has three relevant input clocks. One of them is the reference clock (CLKINP) used to generated the synthesized clock but can also be used as the bypass clock whenever the DPLL enters a bypass mode. It is therefore mandatory. The second one is a fast bypass clock (CLKINPULOW) used when selected as the bypass clock and is optional. The third clock (CLKINPHIF) is explained in the next paragraph.

The DPLL has three output clocks (namely CLKOUT, CLKOUTX2, and CLKOUTHIF). CLKOUT and CLKOUTX2 run at the bypass frequency whenever the DPLL enters a bypass mode. Both of them are generated from the lock frequency divided by a post-divider (namely M2 post-divider). The third clock, CLKOUTHIF, has no automatic bypass capability. It is an output of a post-divider (M3 post-divider) with the input clock selectable between the internal lock clock (Fdpll) and CLKINPHIF input of the PLL through an asynchronous multplexing.

For more information, see the Power, Reset, and Clock Management chapter of the Device TRM.

Table 6-10 summarizes DPLL type described in Section 6.2, DPLLs, DLLs Specifications.

Table 6-10 DPLL Control

DPLL NAME	CONTROLLED BY PRCM
DPLL_CORE	Yes^⁽¹⁾
DPLL_EVE_VID_DSP	Yes^⁽¹⁾
DPLL_GMAC_DSP	Yes^⁽¹⁾
DPLL_PER	Yes^⁽¹⁾
DPLL_DDR	Yes^⁽¹⁾

DPLL is in the always-on domain.

Table 6-11 and summarize the DPLL characteristics and assume testing over recommended operating conditions.

Table 6-11 DPLL Characteristics

NAME	DESCRIPTION	MIN	MAX	UNIT	COMMENTS
f_input	CLKINP input frequency	0.032	52	MHz	F_INP
f_internal	Internal reference frequency	0.15	52	MHz	REFCLK
f_CLKINPHIF	CLKINPHIF input frequency	10	1400	MHz	F_INPHIF
f_CLKINPULOW	CLKINPULOW input frequency	0.001	600	MHz	Bypass mode: f_CLKOUT = f_CLKINPULOW / (M1 + 1) if ulowclken = 1^⁽⁷⁾
f_CLKOUT	CLKOUT output frequency	20^⁽¹⁾	1800^⁽³⁾	MHz	[M / (N + 1)] × F_INP × [1 / M2] (in locked condition)
f_CLKOUTx2	CLKOUTx2 output frequency	40^⁽¹⁾	2200^⁽³⁾	MHz	2 × [M / (N + 1)] × F_INP × [1 / M2] (in locked condition)
f_CLKOUTHIF	CLKOUTHIF output frequency	20^⁽⁴⁾	1400^⁽⁵⁾	MHz	F_INPHIF / M3 if clkinphifsel = 1
f_CLKOUTHIF	CLKOUTHIF output frequency	40^⁽⁴⁾	2200^⁽⁵⁾	MHz	2 × [M / (N + 1)] × F_INP × [1 / M3] if clkinphifsel = 0
f_CLKDCOLDO	DCOCLKLDO output frequency	40	2800	MHz	2 × [M / (N + 1)] × F_INP (in locked condition)
t_lock	Frequency lock time		6 + 350 × REFCLK	µs
p_lock	Phase lock time		6 + 500 × REFCLK	µs
t_relock-L	Relock time—Frequency lock^⁽⁶⁾ (LP relock time from bypass)		6 + 70 × REFCLK	µs	DPLL in LP relock time: lowcurrstdby = 1
p_relock-L	Relock time—Phase lock^⁽⁶⁾ (LP relock time from bypass)		6 + 120 × REFCLK	µs	DPLL in LP relock time: lowcurrstdby = 1
t_relock-F	Relock time—Frequency lock^⁽⁶⁾ (fast relock time from bypass)		3.55 + 70 × REFCLK	µs	DPLL in fast relock time: lowcurrstdby = 0
p_relock-F	Relock time—Phase lock^⁽⁶⁾ (fast relock time from bypass)		3.55 + 120 × REFCLK	µs	DPLL in fast relock time: lowcurrstdby = 0

The minimum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.

For M2 > 1, the minimum frequency on these clocks will further scale down by factor of M2.

The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down by factor of M3.
The maximum frequency on CLKOUTHIF is assuming M3 = 1.
Relock time assumes typical operating conditions, 10°C maximum temperature drift.
Bypass mode: f_CLKOUT = F_INP if ulowclken = 0. For more information, see the Device TRM.