SPRSP62B December 2022 – December 2024 TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
O7 | tc(CLK) | Cycle time, CLK | 1.8V | 7 | ns | |
3.3V | 7.5 | ns | ||||
O8 | tw(CLKL) | Pulse duration, CLK low | ((0.475P(1)) - 0.3) | ns | ||
O9 | Pulse duration, CLK high | ((0.475P(1)) - 0.3) | ns | |||
O10 | ttd(CSn-CLK) | Delay time, CSn active edge to CLK rising edge | 1.8V | ((0.475P(1)) + (0.975M(2)R(4)) + (0.028TD(5)) - 1) | ((0.525P(1)) + (1.025M(2)R(4)) + (0.055TD(5)) + 1) | ns |
3.3V | ((0.475P(1)) + (0.975M(2)R(4)) + (0.028TD(5)) - 1) | ((0.525P(1)) + (1.025M(2)R(4)) + (0.055TD(5)) + 1) | ns | |||
O11 | td(CLK-CSn) | Delay time, CLK rising edge to CSn inactive edge | 1.8V | ((0.475P(1)) + (0.975N(3)R(4)) - (0.055TD(5)) - 1) | ((0.525P(1)) + (1.025N(3)R(4)) - (0.028TD(5)) + 1) | ns |
3.3V | ((0.475P(1)) + (0.975N(3)R(4)) - (0.055TD(5)) - 1) | ((0.525P(1)) + (1.025N(3)R(4)) - (0.028TD(5)) + 1) | ns | |||
O12 | td(CLK-D) | Delay time, CLK active edge to D[i:0] transition(6) | 1.8V | –1.16 | 1.25 | ns |
3.3V | –1.33 | 1.51 | ns |
Section 6.10.5.19.1.2.3, Section 6.10.5.19.1.2.1, Section 6.10.5.19.1.2.2, Section 6.10.5.19.1.2.2, and Figure 6-103 presents timing requirements for OSPI DDR and SDR Mode.