SPRSPB4A June   2024  – December 2024 TDA4APE-Q1 , TDA4VPE-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
      1.      10
      2.      11
    3. 5.3 Signal Descriptions
      1.      13
      2. 5.3.1  ADC
        1. 5.3.1.1 MCU Domain
          1.        16
          2.        17
          3.        18
      3. 5.3.2  CPSW2G
        1. 5.3.2.1 MAIN Domain
          1.        21
        2. 5.3.2.2 MCU Domain
          1.        23
      4. 5.3.3  CPTS
        1. 5.3.3.1 MAIN Domain
          1.        26
        2. 5.3.3.2 MCU Domain
          1.        28
      5. 5.3.4  CSI
        1. 5.3.4.1 MAIN Domain
          1.        31
          2.        32
          3.        33
      6. 5.3.5  DDRSS
        1. 5.3.5.1 MAIN Domain
          1.        36
          2.        37
      7. 5.3.6  Display Port
        1. 5.3.6.1 MAIN Domain
          1.        40
      8. 5.3.7  DMTIMER
        1. 5.3.7.1 MAIN Domain
          1.        43
        2. 5.3.7.2 MCU Domain
          1.        45
      9. 5.3.8  DSI
        1. 5.3.8.1 MAIN Domain
          1.        48
          2.        49
      10. 5.3.9  DSS
        1. 5.3.9.1 MAIN Domain
          1.        52
      11. 5.3.10 ECAP
        1. 5.3.10.1 MAIN Domain
          1.        55
          2.        56
          3.        57
      12. 5.3.11 EPWM
        1. 5.3.11.1 MAIN Domain
          1.        60
          2.        61
          3.        62
          4.        63
          5.        64
          6.        65
          7.        66
      13. 5.3.12 EQEP
        1. 5.3.12.1 MAIN Domain
          1.        69
          2.        70
          3.        71
      14. 5.3.13 GPIO
        1. 5.3.13.1 MAIN Domain
          1.        74
        2. 5.3.13.2 WKUP Domain
          1.        76
      15. 5.3.14 GPMC
        1. 5.3.14.1 MAIN Domain
          1.        79
      16. 5.3.15 HYPERBUS
        1. 5.3.15.1 MCU Domain
          1.        82
      17. 5.3.16 I2C
        1. 5.3.16.1 MAIN Domain
          1.        85
          2.        86
          3.        87
          4.        88
          5.        89
          6.        90
          7.        91
        2. 5.3.16.2 MCU Domain
          1.        93
          2.        94
        3. 5.3.16.3 WKUP Domain
          1.        96
      18. 5.3.17 I3C
        1. 5.3.17.1 MCU Domain
          1.        99
      19. 5.3.18 MCAN
        1. 5.3.18.1 MAIN Domain
          1.        102
          2.        103
          3.        104
          4.        105
          5.        106
          6.        107
          7.        108
          8.        109
          9.        110
          10.        111
          11.        112
          12.        113
          13.        114
          14.        115
          15.        116
          16.        117
          17.        118
          18.        119
        2. 5.3.18.2 MCU Domain
          1.        121
          2.        122
      20. 5.3.19 MCASP
        1. 5.3.19.1 MAIN Domain
          1.        125
          2.        126
          3.        127
          4.        128
          5.        129
      21. 5.3.20 MCSPI
        1. 5.3.20.1 MAIN Domain
          1.        132
          2.        133
          3.        134
          4.        135
          5.        136
          6.        137
          7.        138
        2. 5.3.20.2 MCU Domain
          1.        140
          2.        141
      22. 5.3.21 MDIO
        1. 5.3.21.1 MAIN Domain
          1.        144
          2.        145
        2. 5.3.21.2 MCU Domain
          1.        147
      23. 5.3.22 MMC
        1. 5.3.22.1 MAIN Domain
          1.        150
          2.        151
      24. 5.3.23 OSPI
        1. 5.3.23.1 MCU Domain
          1.        154
          2.        155
      25. 5.3.24 PCIE
        1. 5.3.24.1 MAIN Domain
          1.        158
      26. 5.3.25 SERDES
        1. 5.3.25.1 MAIN Domain
          1.        161
          2.        162
          3.        163
      27. 5.3.26 SGMII
        1. 5.3.26.1 MAIN Domain
          1.        166
      28. 5.3.27 UART
        1. 5.3.27.1 MAIN Domain
          1.        169
          2.        170
          3.        171
          4.        172
          5.        173
          6.        174
          7.        175
          8.        176
          9.        177
          10.        178
        2. 5.3.27.2 MCU Domain
          1.        180
        3. 5.3.27.3 WKUP Domain
          1.        182
      29. 5.3.28 UFS
        1. 5.3.28.1 MAIN Domain
          1.        185
      30. 5.3.29 USB
        1. 5.3.29.1 MAIN Domain
          1.        188
      31. 5.3.30 Emulation and Debug
        1. 5.3.30.1 MAIN Domain
          1.        191
          2.        192
      32. 5.3.31 System and Miscellaneous
        1. 5.3.31.1 Boot Mode Configuration
          1.        195
        2. 5.3.31.2 Clock
          1.        197
          2.        198
        3. 5.3.31.3 EFUSE
          1.        200
        4. 5.3.31.4 System
          1.        202
          2.        203
        5. 5.3.31.5 VMON
          1.        205
      33. 5.3.32 Power
        1.       207
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On-Hour (POH) Limits
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Operating Performance Points
    6. 6.6  Electrical Characteristics
      1. 6.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 6.6.3  HFOSC/LFOSC Electrical Characteristics
      4. 6.6.4  eMMCPHY Electrical Characteristics
      5. 6.6.5  SDIO Electrical Characteristics
      6. 6.6.6  CSI2/DSI D-PHY Electrical Characteristics
      7. 6.6.7  ADC12B Electrical Characteristics
      8. 6.6.8  LVCMOS Electrical Characteristics
      9. 6.6.9  USB2PHY Electrical Characteristics
      10. 6.6.10 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
      11. 6.6.11 UFS M-PHY Electrical Characteristics
      12. 6.6.12 eDP/DP AUX-PHY Electrical Characteristics
      13. 6.6.13 DDR0 Electrical Characteristics
    7. 6.7  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.7.2 Hardware Requirements
      3. 6.7.3 Programming Sequence
      4. 6.7.4 Impact to Your Hardware Warranty
    8. 6.8  Thermal Resistance Characteristics
      1. 6.8.1 Thermal Resistance Characteristics for AND Package
    9. 6.9  Temperature Sensor Characteristics
    10. 6.10 Timing and Switching Characteristics
      1. 6.10.1 Timing Parameters and Information
      2. 6.10.2 Power Supply Sequencing
        1. 6.10.2.1 Power Supply Slew Rate Requirement
        2. 6.10.2.2 Combined MCU and Main Domains Power- Up Sequencing
        3. 6.10.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 6.10.2.4 Isolated MCU and Main Domains Power- Up Sequencing
        5. 6.10.2.5 Isolated MCU and Main Domains Power- Down Sequencing
        6. 6.10.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        7. 6.10.2.7 Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        8. 6.10.2.8 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 6.10.3 System Timing
        1. 6.10.3.1 Reset Timing
        2. 6.10.3.2 Safety Signal Timing
        3. 6.10.3.3 Clock Timing
      4. 6.10.4 Clock Specifications
        1. 6.10.4.1 Input and Output Clocks / Oscillators
          1. 6.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 6.10.4.1.1.1 Load Capacitance
            2. 6.10.4.1.1.2 Shunt Capacitance
          2. 6.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 6.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 6.10.4.1.3.1 Load Capacitance
            2. 6.10.4.1.3.2 Shunt Capacitance
          4. 6.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 6.10.4.1.5 Auxiliary OSC1 Not Used
        2. 6.10.4.2 Output Clocks
        3. 6.10.4.3 PLLs
        4. 6.10.4.4 Module and Peripheral Clocks Frequencies
      5. 6.10.5 Peripherals
        1. 6.10.5.1  ATL
          1. 6.10.5.1.1 ATL_PCLK Timing Requirements
          2. 6.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 6.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 6.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 6.10.5.2  CPSW2G
          1. 6.10.5.2.1 CPSW2G MDIO Interface Timings
          2. 6.10.5.2.2 CPSW2G RMII Timings
            1. 6.10.5.2.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 6.10.5.2.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 6.10.5.2.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 6.10.5.2.3 CPSW2G RGMII Timings
            1. 6.10.5.2.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 6.10.5.2.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 6.10.5.2.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 6.10.5.2.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        3. 6.10.5.3  CSI-2
        4. 6.10.5.4  DDRSS
        5. 6.10.5.5  DSS
        6. 6.10.5.6  eCAP
          1. 6.10.5.6.1 Timing Requirements for eCAP
          2. 6.10.5.6.2 Switching Characteristics for eCAP
        7. 6.10.5.7  EPWM
          1. 6.10.5.7.1 Timing Requirements for eHRPWM
          2. 6.10.5.7.2 Switching Characteristics for eHRPWM
        8. 6.10.5.8  eQEP
          1. 6.10.5.8.1 Timing Requirements for eQEP
          2. 6.10.5.8.2 Switching Characteristics for eQEP
        9. 6.10.5.9  GPIO
          1. 6.10.5.9.1 GPIO Timing Requirements
          2. 6.10.5.9.2 GPIO Switching Characteristics
        10. 6.10.5.10 GPMC
          1. 6.10.5.10.1 GPMC and NOR Flash — Synchronous Mode
            1. 6.10.5.10.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 6.10.5.10.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 6.10.5.10.2 GPMC and NOR Flash — Asynchronous Mode
            1. 6.10.5.10.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 6.10.5.10.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 6.10.5.10.3 GPMC and NAND Flash — Asynchronous Mode
            1. 6.10.5.10.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 6.10.5.10.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 6.10.5.10.4 GPMC0 IOSET
        11. 6.10.5.11 HyperBus
          1. 6.10.5.11.1 Timing Requirements for HyperBus
          2. 6.10.5.11.2 HyperBus 166 MHz Switching Characteristics
          3. 6.10.5.11.3 HyperBus 100 MHz Switching Characteristics
        12. 6.10.5.12 I2C
        13. 6.10.5.13 I3C
        14. 6.10.5.14 MCAN
        15. 6.10.5.15 MCASP
        16. 6.10.5.16 MCSPI
          1. 6.10.5.16.1 MCSPI — Controller Mode
          2. 6.10.5.16.2 MCSPI — Peripheral Mode
        17. 6.10.5.17 MMCSD
          1. 6.10.5.17.1 MMC0 - eMMC Interface
            1. 6.10.5.17.1.1 Legacy SDR Mode
            2. 6.10.5.17.1.2 High Speed SDR Mode
            3. 6.10.5.17.1.3 High Speed DDR Mode
            4. 6.10.5.17.1.4 HS200 Mode
            5. 6.10.5.17.1.5 HS400 Mode
          2. 6.10.5.17.2 MMC1/2 - SD/SDIO Interface
            1. 6.10.5.17.2.1 Default Speed Mode
            2. 6.10.5.17.2.2 High Speed Mode
            3. 6.10.5.17.2.3 UHS–I SDR12 Mode
            4. 6.10.5.17.2.4 UHS–I SDR25 Mode
            5. 6.10.5.17.2.5 UHS–I SDR50 Mode
            6. 6.10.5.17.2.6 UHS–I DDR50 Mode
            7. 6.10.5.17.2.7 UHS–I SDR104 Mode
        18. 6.10.5.18 CPTS
          1. 6.10.5.18.1 CPTS Timing Requirements
          2. 6.10.5.18.2 CPTS Switching Characteristics
        19. 6.10.5.19 OSPI
          1. 6.10.5.19.1 OSPI0/1 PHY Mode
            1. 6.10.5.19.1.1 OSPI0/1 With PHY Data Training
            2. 6.10.5.19.1.2 OSPI Without Data Training
              1. 6.10.5.19.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 6.10.5.19.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 6.10.5.19.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 6.10.5.19.1.2.4 OSPI Switching Characteristics – PHY DDR Mode
          2. 6.10.5.19.2 OSPI0/1 Tap Mode
            1. 6.10.5.19.2.1 OSPI0 Tap SDR Timing
            2. 6.10.5.19.2.2 OSPI0 Tap DDR Timing
        20. 6.10.5.20 OLDI
          1. 6.10.5.20.1 OLDI Switching Characteristics
        21. 6.10.5.21 PCIE
        22. 6.10.5.22 Timers
          1. 6.10.5.22.1 Timing Requirements for Timers
          2. 6.10.5.22.2 Switching Characteristics for Timers
        23. 6.10.5.23 UART
          1. 6.10.5.23.1 Timing Requirements for UART
          2. 6.10.5.23.2 UART Switching Characteristics
        24. 6.10.5.24 USB
      6. 6.10.6 Emulation and Debug
        1. 6.10.6.1 Trace
        2. 6.10.6.2 JTAG
          1. 6.10.6.2.1 JTAG Electrical Data and Timing
            1. 6.10.6.2.1.1 JTAG Timing Requirements
            2. 6.10.6.2.1.2 JTAG Switching Characteristics
  8. 7 Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
        1. 7.1.1.1 Power Distribution Network Implementation Guidance
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG and EMU
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 Hardware Design Guide for JacintoTM 7 Devices
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 LPDDR4 Board Design and Layout Guidelines
      2. 7.2.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 7.2.2.1 No Loopback and Internal Pad Loopback
        2. 7.2.2.2 External Board Loopback
        3. 7.2.2.3 DQS (only available in Octal Flash devices)
      3. 7.2.3 USB VBUS Design Guidelines
      4. 7.2.4 System Power Supply Monitor Design Guidelines using VMON/POK
      5. 7.2.5 High Speed Differential Signal Routing Guidance
      6. 7.2.6 Thermal Solution Guidance
  9. 8 Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • AND|1063
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Device Comparison

Table 4-1 shows the features of the SoC.

Note: To understand what device features are currently supported by TI Software Development Kits (SDKs), see the TDA4VH Software Build Sheet (PROCESSOR-SDK-J742S2).
Table 4-1 Device Comparison
FEATURES(9) REFERENCE
NAME		 TDA4VPE6 TDA4APE6 TDA4VPE4 TDA4APE4
FEATURES
PROCESSORS AND ACCELERATORS
Speed Grades T T T T
Arm Cortex-A72 Microprocessor Subsystem Arm A72 Quad Core(12)
Arm Cortex-R5F Arm R5F Octal Core
Lockstep Optional(1)
Security Management SMS Yes
Security Accelerators SA Yes
C7x Floating Point, Vector DSP C7x DSP Tri Core
Deep Learning Accelerator MMA Dual Core
Graphics Accelerator IMG BXS-4-64 GPU Yes No Yes No
Depth and Motion Processing Accelerators DMPAC Yes
Vision Processing Accelerators VPAC 2 1
Video Encoder / Decoder VENC/ VDEC Enc/Dec 960MP/s Enc/Dec 480MP/s
SAFETY AND SECURITY
Safety Targeted Safety Optional(1) Optional(1)
Device Security Security Optional(2) Optional(2)
AEC-Q100 Qualified Q1 Optional(3) Optional(3)
PROGRAM AND DATA STORAGE
On-Chip Shared Memory (RAM) in MAIN Domain OCSRAM 3x512KB SRAM 3x512KB SRAM
On-Chip Shared Memory (RAM) in MCU Domain MCU_MSRAM 1MB SRAM 1MB SRAM
Multicore Shared Memory Controller MSMC 8MB (On-Chip SRAM with ECC) 4MB (On-Chip SRAM with ECC)
LPDDR4 DDR Subsystem DDRSS0(5) 32-b w/ inline ECC 32-b w/ inline ECC
DDRSS1(5) 32-b w/ inline ECC 32-b w/ inline ECC
DDRSS2(4)(5) No
DDRSS3(4)(5) No
SECDED 7-Bit
General-Purpose Memory Controller GPMC Yes
PERIPHERALS
Display Subsystem DSS Yes Yes
DSI 4L TX 2 2
eDP 4L 1 1
DPI 1 1
Modular Controller Area Network Interface with Full CAN-FD Support MCAN 20 20
General-Purpose I/O GPIO 155 155
Inter-Integrated Circuit Interface I2C 10 10
Improved Inter-Integrated Circuit Interface I3C 1 1
Analog-to-Digital Converter ADC 2 2
Capture Subsystem with Camera Serial Interface (CSI2) CSI2.0 4L RX 3 3
CSI2.0 4L TX 2 2
Multichannel Serial Peripheral Interface MCSPI 11 11
Multichannel Audio Serial Port MCASP0 16 Serializers 16 Serializers
MCASP1 5 Serializers 5 Serializers
MCASP2 5 Serializers 5 Serializers
MCASP3 3 Serializers 3 Serializers
MCASP4 5 Serializers 5 Serializers
MultiMedia Card/ Secure Digital Interface MMCSD0 eMMC
(8-bits)		 eMMC
(8-bits)
MMCSD1 SD/SDIO
(4-bits)		 SD/SDIO
(4-bits)
Universal Flash Storage UFS 2L Yes Yes
Flash Subsystem (FSS) OSPI0 8-bits(8) 8-bits(8)
OSPI1(10) 4-bits 4-bits
HyperBus Yes(8) Yes(8)
4x PCI Express Port with Integrated PHY PCIE 1x4L or 2x2L(6)(11) 1x4L or 2x2L(6)(11)
Ethernet Interfaces MCU CPSW2G RMII or RGMII RMII or RGMII
MAIN CPSW2G RMII or RGMII RMII or RGMII
CPSW9G 4 port SERDES(6)(7) 4 port SERDES(6)(7)
General-Purpose Timers TIMER 30 30
Enhanced High Resolution Pulse-Width Modulator Module eHRPWM 6 6
Enhanced Capture Module eCAP 3 3
Enhanced Quadrature Encoder Pulse Module eQEP 3 3
Universal Asynchronous Receiver and Transmitter UART 12 12
Universal Serial Bus (USB3.1) SuperSpeed Dual-Role-Device (DRD) Ports with SS PHY USB0 Yes(6) Yes(6)
(1) Safety features including R5F Lockstep and SIL/ASIL ratings are only applicable to select part number variants as indicated by the Device Type (Y) identifier in the Nomenclature Description table.
(2) Device security features including Secure Boot and Customer Programmable Keys are applicable to select part number variants as indicated by the Device Type (Y) identifier in the Nomenclature Description table.
(3) AEC-Q100 qualification is applicable to select part number variants as indicated by the Automotive Designator (Q1) identifier in the Nomenclature Description table.
(4) DDRSS2 and DDRSS3 are not available on the 27mm package variant of this SoC. DDR2/DDR3 should be not be used if software compatibility is desired with systems that use the 27mm package
(5) DDRSS0 and DDRSS1 must always be used in incremental order. For instance, when using a single LPDDR component, it must be connected to DDR0_* interface. When using two LPDDR components, they must be connected to DDR0_* and DDR1_* interfaces.
(6) DP, SGMII, USB3.0, and PCIE share total of 8 or 12 SerDes lanes:
  • TDA4xPE6 does not support SERDES2 lanes
  • TDA4xPE4 does not support SERDES0 and SERDES2 lanes
  • TDA4xPE4 has additional muxing limitations for PCIe and SGMII on available SERDES lanes. SERDES and Mux limitations are shown in Pin Attributes Table "VPE4 APE4" column.
(7) TDA4xPE CPSW supports up to 4 ports.
  • TDA4xPE6 allows additional pin muxing flexibility compared to TDA4xPE4
  • TDA4xPE6 allows the system designer to choose based on any available PORTS, but must limit the total number of ports used to four or fewer
  • TDA4xPE4 reduces the pin muxing availability as shown in Pin Attributes Table "VPE4 APE4" column
The following instances, signals, and modes of operation are available across the 8 ports:
  • PORT1 Signals: SGMII1, Modes: One of 5Gb, 10Gb USXGMII/XFI, 2.5Gb SGMII/XAUI, 1Gb SGMII, 5Gb QSGMII
  • PORT2 Signals: SGMII2, Modes: One of 5Gb, 10Gb USXGMII/XFI, 2.5Gb SGMII/XAUI, 1Gb SGMII, 5Gb QSGMII
  • PORTn (n=3 thru 8) Signals: SGMIIn, Modes: One of 2.5Gb SGMII/XAUI, 1Gb SGMII, 5Gb QSGMII
If QSGMII is used on any SGMII Port 1 thru 4, then SGMII1/2/3/4 cannot be used for Ethernet functionality since all 4 internal CPSW ports map to the selected QSGMII SERDES port.
If QSGMII is used on any SGMII Port 5 thru 8, then SGMII5/6/7/8 cannot be used for Ethernet functionality since all 4 internal CPSW ports map to the selected QSGMII SERDES port.
(8) Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus and OSPI1.
(9) XJ742S2 is the base part number for the superset device. Software should constrain the features used to match the intended production device.
(10) OSPI1 module only pins out 4 pins and is referred to as QSPI in some contexts.
(11) TDA4xPE PCIe supports 1x4L or 2x2L options.
  • TDA4xPE6 allows additional pin muxing flexibility compared to the TDA4xPE4 device
  • TDA4xPE6 allows the system designer to choose any available PCIe instances or available PORTS but must limit to a maximum of 1x4L or 2x2L
  • TDA4xPE4 reduces the pin muxing availability as shown in Pin Attributes Table "VPE4 APE4" column
(12) The A72SS Quad Core variant provides a single quad core cluster, namely A72SS0_CORE[3:0].