SPRSPB4A June   2024  – December 2024 TDA4APE-Q1 , TDA4VPE-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
      1.      10
      2.      11
    3. 5.3 Signal Descriptions
      1.      13
      2. 5.3.1  ADC
        1. 5.3.1.1 MCU Domain
          1.        16
          2.        17
          3.        18
      3. 5.3.2  CPSW2G
        1. 5.3.2.1 MAIN Domain
          1.        21
        2. 5.3.2.2 MCU Domain
          1.        23
      4. 5.3.3  CPTS
        1. 5.3.3.1 MAIN Domain
          1.        26
        2. 5.3.3.2 MCU Domain
          1.        28
      5. 5.3.4  CSI
        1. 5.3.4.1 MAIN Domain
          1.        31
          2.        32
          3.        33
      6. 5.3.5  DDRSS
        1. 5.3.5.1 MAIN Domain
          1.        36
          2.        37
      7. 5.3.6  Display Port
        1. 5.3.6.1 MAIN Domain
          1.        40
      8. 5.3.7  DMTIMER
        1. 5.3.7.1 MAIN Domain
          1.        43
        2. 5.3.7.2 MCU Domain
          1.        45
      9. 5.3.8  DSI
        1. 5.3.8.1 MAIN Domain
          1.        48
          2.        49
      10. 5.3.9  DSS
        1. 5.3.9.1 MAIN Domain
          1.        52
      11. 5.3.10 ECAP
        1. 5.3.10.1 MAIN Domain
          1.        55
          2.        56
          3.        57
      12. 5.3.11 EPWM
        1. 5.3.11.1 MAIN Domain
          1.        60
          2.        61
          3.        62
          4.        63
          5.        64
          6.        65
          7.        66
      13. 5.3.12 EQEP
        1. 5.3.12.1 MAIN Domain
          1.        69
          2.        70
          3.        71
      14. 5.3.13 GPIO
        1. 5.3.13.1 MAIN Domain
          1.        74
        2. 5.3.13.2 WKUP Domain
          1.        76
      15. 5.3.14 GPMC
        1. 5.3.14.1 MAIN Domain
          1.        79
      16. 5.3.15 HYPERBUS
        1. 5.3.15.1 MCU Domain
          1.        82
      17. 5.3.16 I2C
        1. 5.3.16.1 MAIN Domain
          1.        85
          2.        86
          3.        87
          4.        88
          5.        89
          6.        90
          7.        91
        2. 5.3.16.2 MCU Domain
          1.        93
          2.        94
        3. 5.3.16.3 WKUP Domain
          1.        96
      18. 5.3.17 I3C
        1. 5.3.17.1 MCU Domain
          1.        99
      19. 5.3.18 MCAN
        1. 5.3.18.1 MAIN Domain
          1.        102
          2.        103
          3.        104
          4.        105
          5.        106
          6.        107
          7.        108
          8.        109
          9.        110
          10.        111
          11.        112
          12.        113
          13.        114
          14.        115
          15.        116
          16.        117
          17.        118
          18.        119
        2. 5.3.18.2 MCU Domain
          1.        121
          2.        122
      20. 5.3.19 MCASP
        1. 5.3.19.1 MAIN Domain
          1.        125
          2.        126
          3.        127
          4.        128
          5.        129
      21. 5.3.20 MCSPI
        1. 5.3.20.1 MAIN Domain
          1.        132
          2.        133
          3.        134
          4.        135
          5.        136
          6.        137
          7.        138
        2. 5.3.20.2 MCU Domain
          1.        140
          2.        141
      22. 5.3.21 MDIO
        1. 5.3.21.1 MAIN Domain
          1.        144
          2.        145
        2. 5.3.21.2 MCU Domain
          1.        147
      23. 5.3.22 MMC
        1. 5.3.22.1 MAIN Domain
          1.        150
          2.        151
      24. 5.3.23 OSPI
        1. 5.3.23.1 MCU Domain
          1.        154
          2.        155
      25. 5.3.24 PCIE
        1. 5.3.24.1 MAIN Domain
          1.        158
      26. 5.3.25 SERDES
        1. 5.3.25.1 MAIN Domain
          1.        161
          2.        162
          3.        163
      27. 5.3.26 SGMII
        1. 5.3.26.1 MAIN Domain
          1.        166
      28. 5.3.27 UART
        1. 5.3.27.1 MAIN Domain
          1.        169
          2.        170
          3.        171
          4.        172
          5.        173
          6.        174
          7.        175
          8.        176
          9.        177
          10.        178
        2. 5.3.27.2 MCU Domain
          1.        180
        3. 5.3.27.3 WKUP Domain
          1.        182
      29. 5.3.28 UFS
        1. 5.3.28.1 MAIN Domain
          1.        185
      30. 5.3.29 USB
        1. 5.3.29.1 MAIN Domain
          1.        188
      31. 5.3.30 Emulation and Debug
        1. 5.3.30.1 MAIN Domain
          1.        191
          2.        192
      32. 5.3.31 System and Miscellaneous
        1. 5.3.31.1 Boot Mode Configuration
          1.        195
        2. 5.3.31.2 Clock
          1.        197
          2.        198
        3. 5.3.31.3 EFUSE
          1.        200
        4. 5.3.31.4 System
          1.        202
          2.        203
        5. 5.3.31.5 VMON
          1.        205
      33. 5.3.32 Power
        1.       207
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On-Hour (POH) Limits
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Operating Performance Points
    6. 6.6  Electrical Characteristics
      1. 6.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 6.6.3  HFOSC/LFOSC Electrical Characteristics
      4. 6.6.4  eMMCPHY Electrical Characteristics
      5. 6.6.5  SDIO Electrical Characteristics
      6. 6.6.6  CSI2/DSI D-PHY Electrical Characteristics
      7. 6.6.7  ADC12B Electrical Characteristics
      8. 6.6.8  LVCMOS Electrical Characteristics
      9. 6.6.9  USB2PHY Electrical Characteristics
      10. 6.6.10 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
      11. 6.6.11 UFS M-PHY Electrical Characteristics
      12. 6.6.12 eDP/DP AUX-PHY Electrical Characteristics
      13. 6.6.13 DDR0 Electrical Characteristics
    7. 6.7  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.7.2 Hardware Requirements
      3. 6.7.3 Programming Sequence
      4. 6.7.4 Impact to Your Hardware Warranty
    8. 6.8  Thermal Resistance Characteristics
      1. 6.8.1 Thermal Resistance Characteristics for AND Package
    9. 6.9  Temperature Sensor Characteristics
    10. 6.10 Timing and Switching Characteristics
      1. 6.10.1 Timing Parameters and Information
      2. 6.10.2 Power Supply Sequencing
        1. 6.10.2.1 Power Supply Slew Rate Requirement
        2. 6.10.2.2 Combined MCU and Main Domains Power- Up Sequencing
        3. 6.10.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 6.10.2.4 Isolated MCU and Main Domains Power- Up Sequencing
        5. 6.10.2.5 Isolated MCU and Main Domains Power- Down Sequencing
        6. 6.10.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        7. 6.10.2.7 Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        8. 6.10.2.8 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 6.10.3 System Timing
        1. 6.10.3.1 Reset Timing
        2. 6.10.3.2 Safety Signal Timing
        3. 6.10.3.3 Clock Timing
      4. 6.10.4 Clock Specifications
        1. 6.10.4.1 Input and Output Clocks / Oscillators
          1. 6.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 6.10.4.1.1.1 Load Capacitance
            2. 6.10.4.1.1.2 Shunt Capacitance
          2. 6.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 6.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 6.10.4.1.3.1 Load Capacitance
            2. 6.10.4.1.3.2 Shunt Capacitance
          4. 6.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 6.10.4.1.5 Auxiliary OSC1 Not Used
        2. 6.10.4.2 Output Clocks
        3. 6.10.4.3 PLLs
        4. 6.10.4.4 Module and Peripheral Clocks Frequencies
      5. 6.10.5 Peripherals
        1. 6.10.5.1  ATL
          1. 6.10.5.1.1 ATL_PCLK Timing Requirements
          2. 6.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 6.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 6.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 6.10.5.2  CPSW2G
          1. 6.10.5.2.1 CPSW2G MDIO Interface Timings
          2. 6.10.5.2.2 CPSW2G RMII Timings
            1. 6.10.5.2.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 6.10.5.2.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 6.10.5.2.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 6.10.5.2.3 CPSW2G RGMII Timings
            1. 6.10.5.2.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 6.10.5.2.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 6.10.5.2.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 6.10.5.2.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        3. 6.10.5.3  CSI-2
        4. 6.10.5.4  DDRSS
        5. 6.10.5.5  DSS
        6. 6.10.5.6  eCAP
          1. 6.10.5.6.1 Timing Requirements for eCAP
          2. 6.10.5.6.2 Switching Characteristics for eCAP
        7. 6.10.5.7  EPWM
          1. 6.10.5.7.1 Timing Requirements for eHRPWM
          2. 6.10.5.7.2 Switching Characteristics for eHRPWM
        8. 6.10.5.8  eQEP
          1. 6.10.5.8.1 Timing Requirements for eQEP
          2. 6.10.5.8.2 Switching Characteristics for eQEP
        9. 6.10.5.9  GPIO
          1. 6.10.5.9.1 GPIO Timing Requirements
          2. 6.10.5.9.2 GPIO Switching Characteristics
        10. 6.10.5.10 GPMC
          1. 6.10.5.10.1 GPMC and NOR Flash — Synchronous Mode
            1. 6.10.5.10.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 6.10.5.10.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 6.10.5.10.2 GPMC and NOR Flash — Asynchronous Mode
            1. 6.10.5.10.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 6.10.5.10.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 6.10.5.10.3 GPMC and NAND Flash — Asynchronous Mode
            1. 6.10.5.10.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 6.10.5.10.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 6.10.5.10.4 GPMC0 IOSET
        11. 6.10.5.11 HyperBus
          1. 6.10.5.11.1 Timing Requirements for HyperBus
          2. 6.10.5.11.2 HyperBus 166 MHz Switching Characteristics
          3. 6.10.5.11.3 HyperBus 100 MHz Switching Characteristics
        12. 6.10.5.12 I2C
        13. 6.10.5.13 I3C
        14. 6.10.5.14 MCAN
        15. 6.10.5.15 MCASP
        16. 6.10.5.16 MCSPI
          1. 6.10.5.16.1 MCSPI — Controller Mode
          2. 6.10.5.16.2 MCSPI — Peripheral Mode
        17. 6.10.5.17 MMCSD
          1. 6.10.5.17.1 MMC0 - eMMC Interface
            1. 6.10.5.17.1.1 Legacy SDR Mode
            2. 6.10.5.17.1.2 High Speed SDR Mode
            3. 6.10.5.17.1.3 High Speed DDR Mode
            4. 6.10.5.17.1.4 HS200 Mode
            5. 6.10.5.17.1.5 HS400 Mode
          2. 6.10.5.17.2 MMC1/2 - SD/SDIO Interface
            1. 6.10.5.17.2.1 Default Speed Mode
            2. 6.10.5.17.2.2 High Speed Mode
            3. 6.10.5.17.2.3 UHS–I SDR12 Mode
            4. 6.10.5.17.2.4 UHS–I SDR25 Mode
            5. 6.10.5.17.2.5 UHS–I SDR50 Mode
            6. 6.10.5.17.2.6 UHS–I DDR50 Mode
            7. 6.10.5.17.2.7 UHS–I SDR104 Mode
        18. 6.10.5.18 CPTS
          1. 6.10.5.18.1 CPTS Timing Requirements
          2. 6.10.5.18.2 CPTS Switching Characteristics
        19. 6.10.5.19 OSPI
          1. 6.10.5.19.1 OSPI0/1 PHY Mode
            1. 6.10.5.19.1.1 OSPI0/1 With PHY Data Training
            2. 6.10.5.19.1.2 OSPI Without Data Training
              1. 6.10.5.19.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 6.10.5.19.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 6.10.5.19.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 6.10.5.19.1.2.4 OSPI Switching Characteristics – PHY DDR Mode
          2. 6.10.5.19.2 OSPI0/1 Tap Mode
            1. 6.10.5.19.2.1 OSPI0 Tap SDR Timing
            2. 6.10.5.19.2.2 OSPI0 Tap DDR Timing
        20. 6.10.5.20 OLDI
          1. 6.10.5.20.1 OLDI Switching Characteristics
        21. 6.10.5.21 PCIE
        22. 6.10.5.22 Timers
          1. 6.10.5.22.1 Timing Requirements for Timers
          2. 6.10.5.22.2 Switching Characteristics for Timers
        23. 6.10.5.23 UART
          1. 6.10.5.23.1 Timing Requirements for UART
          2. 6.10.5.23.2 UART Switching Characteristics
        24. 6.10.5.24 USB
      6. 6.10.6 Emulation and Debug
        1. 6.10.6.1 Trace
        2. 6.10.6.2 JTAG
          1. 6.10.6.2.1 JTAG Electrical Data and Timing
            1. 6.10.6.2.1.1 JTAG Timing Requirements
            2. 6.10.6.2.1.2 JTAG Switching Characteristics
  8. 7 Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
        1. 7.1.1.1 Power Distribution Network Implementation Guidance
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG and EMU
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 Hardware Design Guide for JacintoTM 7 Devices
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 LPDDR4 Board Design and Layout Guidelines
      2. 7.2.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 7.2.2.1 No Loopback and Internal Pad Loopback
        2. 7.2.2.2 External Board Loopback
        3. 7.2.2.3 DQS (only available in Octal Flash devices)
      3. 7.2.3 USB VBUS Design Guidelines
      4. 7.2.4 System Power Supply Monitor Design Guidelines using VMON/POK
      5. 7.2.5 High Speed Differential Signal Routing Guidance
      6. 7.2.6 Thermal Solution Guidance
  9. 8 Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • AND|1063
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 5-117 Power Supply Signal Descriptions
SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] AND PIN [4]
CAP_VDDS0 (1) CAP External Capacitor Connection T27
CAP_VDDS0_MCU (1) CAP External Capacitor Connection J25
CAP_VDDS1_MCU (1) CAP External Capacitor Connection J23
CAP_VDDS2 (1) CAP External Capacitor Connection P27
CAP_VDDS2_MCU (1) CAP External Capacitor Connection J24
CAP_VDDS5 (1) CAP External Capacitor Connection M27
VDDAR_CORE PWR Core RAM Supply AA22, AD13, AD16, AD19, AE26, AE9, P23, Y25
VDDAR_CPU PWR CPU RAM Supply AA14, AA16, AA18, AC10, K19, L21, P13, R18, U12, U19, V17, V9, Y11
VDDAR_MCU PWR MCU RAM Supply K25, L22
VDDA_0P8_DSITX PWR Analog Supply for DSITX AG22
VDDA_0P8_DSITX_C PWR DSITX Clock Supply AG23
VDDA_0P8_UFS PWR UFS 0.8V Supply AF9
VDDA_0P8_USB PWR USB 0.8V Supply AG17
VDDA_0P8_CSIRX2 PWR Analog Supply for CSIRX AG26
VDDA_0P8_CSIRX0_1 PWR Analog Supply for CSIRX AG24
VDDA_0P8_DLL_MMC0 PWR MMC DLL Analog Supply AD7
VDDA_0P8_PLL_DDR0 PWR DDR de-skew PLL Analog Supply P8
VDDA_0P8_PLL_DDR1 PWR DDR de-skew PLL Analog Supply J11
VDDA_0P8_SERDES4 PWR SERDES 0.8V Supply AG15, AG16
VDDA_0P8_SERDES0_1 PWR SERDES 0.8V Supply AF12, AG10, AG13
VDDA_0P8_SERDES_C4 PWR SERDES 0.8V Clock Supply AE15, AF16
VDDA_0P8_SERDES_C0_1 PWR SERDES 0.8V Clock Supply AF10, AF13
VDDA_1P8_DSITX PWR Analog Supply for DSITX AF22, AF23
VDDA_1P8_UFS PWR UFS 1.8V Supply AG8
VDDA_1P8_USB PWR USB 1.8V Supply AH19
VDDA_1P8_CSIRX2 PWR Analog Supply for CSIRX AF27, AG27
VDDA_1P8_CSIRX0_1 PWR Analog Supply for CSIRX AF25, AF26
VDDA_1P8_SERDES4 PWR SERDES 1.8V Supply AF15
VDDA_1P8_SERDES0_1 PWR SERDES 1.8V Supply AG11, AG12
VDDA_1P8_SERDES2_4 PWR SERDES 1.8V Supply AG21
VDDA_3P3_USB PWR USB 3.3V Supply AF17
VDDA_ADC0 PWR ADC0 Analog Supply J28
VDDA_ADC1 PWR ADC1 Analog Supply K28
VDDA_MCU_PLLGRP0 PWR Analog Supply for MCU PLL Group 0 K26
VDDA_MCU_TEMP PWR Analog Supply for MCU temperature sensor K24
VDDA_OSC1 PWR HFOSC1 Supply L27
VDDA_PLLGRP0 PWR Analog Supply for MAIN PLL Group 0 W25
VDDA_PLLGRP1 PWR Analog Supply for MAIN PLL Group 1 V25
VDDA_PLLGRP2 PWR Analog Supply for MAIN PLL Group 2 AE11
VDDA_PLLGRP5 PWR Analog Supply for MAIN PLL Group 5 T12
VDDA_PLLGRP6 PWR Analog Supply for MAIN PLL Group 6 N19
VDDA_PLLGRP7 PWR Analog Supply for MAIN PLL Group 7 M10
VDDA_PLLGRP8 PWR Analog Supply for MAIN PLL Group 8 K13
VDDA_PLLGRP9 PWR Analog Supply for MAIN PLL Group 9 V24
VDDA_PLLGRP10 PWR Analog Supply for MAIN PLL Group 10 AD20
VDDA_PLLGRP12 PWR Analog Supply for MAIN PLL Group 12 W21
VDDA_PLLGRP13 PWR Analog Supply for MAIN PLL Group 13 Y24
VDDA_POR_WKUP PWR WKUP domain Analog Supply L26
VDDA_TEMP0 PWR Analog Supply for temperature sensor 0 V26
VDDA_TEMP1 PWR Analog Supply for temperature sensor 1 K10
VDDA_TEMP2 PWR Analog Supply for temperature sensor 2 U21
VDDA_TEMP3 PWR Analog Supply for temperature sensor 3 AC11
VDDA_TEMP4 PWR Analog Supply for temperature sensor 4 AB16
VDDA_WKUP PWR Oscillator Supply for WKUP domain J27
VDDSHV0 PWR IO Power Supply T28
VDDSHV0_MCU PWR IO Power Supply H27
VDDSHV1_MCU PWR IO Power Supply G22, H23
VDDSHV2 PWR IO Power Supply N28, P28
VDDSHV2_MCU PWR IO Power Supply G24, H25
VDDSHV5 PWR IO Power Supply N27
VDDS_DDR PWR DDR PHY IO Supply A2, AH1, G10, G12, G14, G16, G18, H11, H13, H15, H17, H9, J10, J14, J16, J8, K7, L8, M7, P7, R8
VDDS_DDR_C0 PWR IO Power Supply for DDR Clock N8
VDDS_DDR_C1 PWR IO Power Supply for DDR Clock J12
VDDS_MMC0 PWR MMC0 PHY IO Supply AE8, AF7
VDD_CORE PWR MAIN domain core Supply AA24, AA26, AA28, AB23, AB25, AB27, AC22, AC24, AC26, AC28, AD11, AD15, AD17, AD21, AD23, AD25, AD27, AE10, AE12, AE14, AE16, AE18, AE20, AE22, AE24, AE28, AF19, K11, K15, K17, K9, L10, L12, L14, L16, M11, M13, M15, M17, M9, N10, N12, N14, N16, N22, N24, N26, P11, P25, P9, R10, R22, R24, R26, T23, T25, U22, U24, U26, U28, V23, V27, W22, W24, W26, W28, Y23, Y27
VDD_CPU PWR CPU core Supply AA10, AA12, AA20, AA8, AB11, AB13, AB15, AB17, AB19, AB21, AB9, AC12, AC14, AC16, AC18, AC20, AC8, AD9, H19, H21, J18, J20, L18, L20, M19, N18, N20, P15, P17, P19, P21, R12, R20, T11, T17, T19, T21, T9, U10, U18, U20, U8, V11, V19, V21, W10, W12, W18, W20, W8, Y17, Y19, Y21, Y9
VDD_MCU PWR MCU core Supply J22, K21, K23, L24, M21, M23, M25
VDD_MCU_WAKE1 PWR Core Supply for MCU daisy chain J26
VDD_WAKE0 PWR Core Supply for MAIN domain daisy chain R27
VSS GND Ground A1, A23, A25, A27, A29, A31, A4, A7, AA11, AA13, AA15, AA17, AA19, AA2, AA21, AA23, AA25, AA27, AA29, AA31, AA33, AA5, AA9, AB1, AB10, AB12, AB14, AB18, AB20, AB22, AB24, AB26, AB28, AB30, AB32, AB4, AB8, AC13, AC15, AC17, AC19, AC2, AC21, AC23, AC25, AC27, AC5, AC9, AD10, AD12, AD14, AD18, AD22, AD24, AD26, AD28, AD29, AD3, AD31, AD33, AD6, AD8, AE1, AE13, AE17, AE19, AE21, AE23, AE25, AE27, AE30, AE32, AE4, AE7, AF11, AF14, AF18, AF2, AF20, AF21, AF24, AF28, AF5, AF8, AG14, AG18, AG20, AG25, AG28, AG29, AG3, AG31, AG33, AG6, AG9, AH12, AH15, AH18, AH21, AH24, AH26, AH28, AH30, AH5, AJ11, AJ14, AJ17, AJ20, AJ23, AJ26, AJ29, AJ32, AJ6, AJ8, AK10, AK13, AK16, AK19, AK22, AK25, AK28, AK31, AK4, AK7, AL12, AL15, AL18, AL21, AL24, AL27, AL3, AL30, AL33, AL6, AL9, AM11, AM14, AM17, AM2, AM20, AM23, AM26, AM29, AM32, AM33, AM5, AM8, AN1, AN10, AN13, AN16
VSS (continued) GND Ground AN19, AN22, AN25, AN28, AN31, AN32, AN4, AN7, B22, B24, B26, B28, B3, B30, B32, B6, C11, C13, C15, C17, C2, C21, C23, C25, C27, C29, C31, C33, C5, D1, D26, D28, D30, D32, D4, D7, E23, E25, E27, E29, E3, E31, E6, E8, F14, F16, F18, F2, F20, F22, F24, F5, F7, G1, G11, G13, G15, G17, G19, G21, G23, G25, G27, G4, G9, H10, H12, H14, H16, H18, H2, H20, H22, H24, H26, H28, H5, H8, J1, J13, J15, J17, J19, J21, J6, J7, J9, K12, K14, K16, K18, K2, K20, K22, K27, K29, K5, K8, L11, L13, L15, L17, L19, L23, L3, L6, L7, L9, M1, M12, M14, M16, M18, M20, M22, M24, M28, M4, M8, N11, N13, N15, N17, N2, N21, N23, N25, N29, N5, N7, N9, P10, P12, P14, P16, P18, P20, P22, P24, P26, P3, R11, R17, R19, R21, R23, R25, R28, R3, R6
VSS (continued) GND Ground R9, T10, T18, T2, T20, T22, T24, T26, T5, T8, U1, U11, U17, U23, U25, U27, U29, U33, U4, U7, U9, V10, V12, V18, V20, V22, V28, V3, V6, V8, W11, W17, W19, W2, W23, W27, W29, W5, W9, Y1, Y10, Y12, Y18, Y20, Y22, Y26, Y28, Y6, Y8
(1) This pin must always be connected via a 1-μF ±10% capacitor to VSS.