Table 6-4 and Figure 6-5 describes the device power-up sequencing.
Note: The power supply sequencing
requirements defined in this section does not include entry or exit from low power
modes. See
the
Partial IO Power
Sequencing section for more information on the requirements for
entering or exiting from Partial IO low power mode.
Note: All power rails must be turned off and decay below 300mV before initiating a new
power-up sequence anytime a power rail drops below the minimum value defined in
Recommended Operating Conditions. The only exception is when
entering/exiting Partial IO low power mode with VDDSHV_CANUART and VDD_CANUART
sourced from an always on power source. For this use case the VDDSHV_CANUART and
VDD_CANUART power rails are allowed to remain on.
Table 6-4 Power-Up Sequencing – Supply /
Signal Assignments See: Figure 6-5
WAVEFORM |
SUPPLY / SIGNAL NAME |
A |
VSYS(1), VMON_VSYS(2) |
B |
VDDSHV_CANUART(3), VDDSHV_MCU(3), VDDSHV0(3), VDDSHV1(3), VDDSHV2(3), VDDSHV3(3), VDDA_3P3_USB, VMON_3P3_SOC(4) |
C |
VDDSHV_CANUART(5), VDDSHV_MCU(5), VDDSHV0(5), VDDSHV1(5), VDDSHV2(5), VDDSHV3(5), VDDS_MMC0, VDDA_MCU, VDDS_OSC0, VDDA_PLL0, VDDA_PLL1, VDDA_PLL2,
VDDA_1P8_CSI_DSI, VDDA_1P8_OLDI0, VDDA_1P8_USB, VDDA_TEMP0,
VDDA_TEMP1, VMON_1P8_SOC(6) |
D |
VDDSHV5(7), VDDSHV6(7) |
E |
VDDS_DDR(8), VDDS_DDR_C(8) |
F |
VDD_CANUART(9) |
G |
VDD_CANUART(10), VDD_CORE(10)(12), VDDA_CORE_CSI_DSI(10), VDDA_CORE_DSI_CLK(10), VDDA_CORE_USB0(10), VDDA_DDR_PLL0(10) |
H |
VDD_CANUART(11), VDD_CORE(11)(12), VDDA_CORE_CSI_DSI(11), VDDA_CORE_DSI_CLK(11), VDDA_CORE_USB0(11), VDDA_DDR_PLL0(11), VDDR_CORE(12), VDD_MMC0, VDDA_0P85_DLL_MMC0 |
I |
VPP(13) |
J |
MCU_PORz |
K |
MCU_OSC0_XI, MCU_OSC0_XO |
(1) VSYS represents the name of a supply which sources power to the entire system.
This supply is expected to be a pre-regulated supply that sources power
management devices which source all other supplies.
(2) VMON_VSYS input is used to
monitor VSYS via an external resistor divider circuit. For more information, see
the
Section 8.2.4,
System Power Supply Monitor Design Guidelines.
(3) VDDSHV_CANUART, VDDSHV_MCU, and
VDDSHVx [x=0-3] are dual voltage IO supplies which can be operated at 1.8V or
3.3V depending on the application requirements.VDDSHV_CANUART shall be connected to an always-on power source when using
Partial IO low power mode, or connected to any valid IO power source when not
using Partial IO low power mode. When VDDSHV_CANUART is not connected to an
always-on power source and is operating at 3.3V, it shall be ramped up with
other 3.3V supplies during the 3.3V ramp period defined by this waveform.When any of the VDDSHV_MCU and VDDSHVx [x=0-3]
IO supplies are operating at 3.3V, they shall be ramped up with other 3.3V
supplies during the 3.3V ramp period defined by this waveform.
(4) The VMON_3P3_SOC input is used to monitor supply voltage and shall be connected
to the respective 3.3V supply source.
(5) VDDSHV_CANUART, VDDSHV_MCU, and
VDDSHVx [x=0-3] are dual voltage IO supplies which can be operated at 1.8V or
3.3V depending on the application requirements.VDDSHV_CANUART shall be connected to an always-on power source when using
Partial IO low power mode, or connected to any valid IO power source when not
using Partial IO low power mode. When VDDSHV_CANUART is not connected to an
always-on power source and is operating at 1.8V, it shall be ramped up with
other 1.8V supplies during the 1.8V ramp period defined by this waveform.When any of the VDDSHV_MCU and VDDSHVx [x=0-3]
IO supplies are operating at 1.8V, they shall be ramped up with other 1.8V
supplies during the 1.8V ramp period defined by this waveform.
(6) The VMON_1P8_SOC input is used to monitor supply voltage and shall be connected
to the respective 1.8V supply source.
(7) VDDSHV5, and VDDSHV6 were
designed to support power-up, power-down, or dynamic voltage change without any
dependency on other power rails. This capability is required to support UHS-I SD
Cards.
(8) VDDS_DDR and VDDS_DDR_C are expected to be powered by the same source such that
they ramp together.
(9) VDD_CANUART shall be connected to
an always-on power source when using Partial IO low power mode.When VDD_CANUART is connected to an always-on
power source, the potential applied to VDD_CORE must never be greater than the
potential applied to VDD_CANUART + 0.18V during power-up or power-down. This
requires VDD_CANUART to ramp up before and ramp down after VDD_CORE. VDD_CANUART
does not have any ramp requirements beyond the one defined for VDD_CORE.
(10) VDD_CANUART shall be connected to
the same power source as VDD_CORE, VDDA_CORE_CSI_DSI, VDDA_CORE_DSI_CLK,
VDDA_CORE_USB, and VDDA_DDR_PLL0 when not using Partial IO low power mode.VDD_CANUART, VDD_CORE, VDDA_CORE_CSI_DSI,
VDDA_CORE_DSI_CLK, VDDA_CORE_USB, and VDDA_DDR_PLL0 can be operated at 0.75V or
0.85V. When these supplies are operating at 0.75V, they shall be ramped up prior
to VDDR_CORE as defined by this waveform.
(11) VDD_CANUART shall be connected to
the same power source as VDD_CORE, VDDA_CORE_CSI_DSI, VDDA_CORE_DSI_CLK,
VDDA_CORE_USB, and VDDA_DDR_PLL0 when not using Partial IO low power mode.VDD_CANUART, VDD_CORE, VDDA_CORE_CSI_DSI,
VDDA_CORE_DSI_CLK, VDDA_CORE_USB, and VDDA_DDR_PLL0 can be operated at 0.75V or
0.85V. When these supplies are operating at 0.85V, they shall be powered from
the same source as VDDR_CORE and ramped during the 0.85V ramp period defined by
this waveform.
(12) The potential applied to VDDR_CORE must never be greater than the potential
applied to VDD_CORE + 0.18V during power-up or power-down. This requires
VDD_CORE to ramp up before and ramp down after VDDR_CORE when VDD_CORE is
operating at 0.75V. VDD_CORE does not have any ramp requirements beyond the one
defined for VDDR_CORE.VDD_CORE and VDDR_CORE are
expected to be powered by the same source so they ramp together when VDD_CORE is
operating at 0.85V.
(13) VPP is the 1.8V eFuse programming supply, which shall be left floating (HiZ) or
grounded during power-up/down sequences and during normal device operation. This
supply shall only be sourced while programming eFuse.