6.9.3.3 Clock Timing

Tables and figures provided in this section define timing conditions, timing requirements, and switching characteristics for clock signals.

Table 6-18 Clock Timing Conditions

PARAMETER			MIN	MAX	UNIT
INPUT CONDITIONS
SR_I	Input slew rate		0.5		V/ns
OUTPUT CONDITIONS
C_L	Output load capacitance	5ns ≤ t_c < 8ns		5	pF
		8ns ≤ t_c < 20ns		10	pF
		20ns ≤ t_c		30	pF

Table 6-19 Clock Timing Requirements see Figure 6-14

NO.			MIN	MAX	UNIT
CLK1	t_{c(EXT_REFCLK1)}	Cycle time minimum, EXT_REFCLK1	10		ns
CLK2	t_{w(EXT_REFCLK1H)}	Pulse Duration, EXT_REFCLK1 high	E*0.45⁽¹⁾	E*0.55⁽¹⁾	ns
CLK3	t_{w(EXT_REFCLK1L)}	Pulse Duration, EXT_REFCLK1 low	E*0.45⁽¹⁾	E*0.55⁽¹⁾	ns
CLK1	t_{c(MCU_EXT_REFCLK0)}	Cycle time minimum, MCU_EXT_REFCLK0	10		ns
CLK2	t_{w(MCU_EXT_REFCLK0H)}	Pulse Duration, MCU_EXT_REFCLK0 high	F*0.45⁽²⁾	F*0.55⁽²⁾	ns
CLK3	t_{w(MCU_EXT_REFCLK0L)}	Pulse Duration, MCU_EXT_REFCLK0 low	F*0.45⁽²⁾	F*0.55⁽²⁾	ns
CLK1	t_{c(AUDIO_EXT_REFCLK0)}	Cycle time minimum, AUDIO_EXT_REFCLK0	20		ns
CLK2	t_{w(AUDIO_EXT_REFCLK0H)}	Pulse Duration, AUDIO_EXT_REFCLK0 high	G*0.45⁽³⁾	G*0.55⁽³⁾	ns
CLK3	t_{w(AUDIO_EXT_REFCLK0L)}	Pulse Duration, AUDIO_EXT_REFCLK0 low	G*0.45⁽³⁾	G*0.55⁽³⁾	ns
CLK1	t_{c(AUDIO_EXT_REFCLK1)}	Cycle time minimum, AUDIO_EXT_REFCLK1	20		ns
CLK2	t_{w(AUDIO_EXT_REFCLK1H)}	Pulse Duration, AUDIO_EXT_REFCLK1 high	H*0.45⁽⁴⁾	H*0.55⁽⁴⁾	ns
CLK3	t_{w(AUDIO_EXT_REFCLK1L)}	Pulse Duration, AUDIO_EXT_REFCLK1 low	H*0.45⁽⁴⁾	H*0.55⁽⁴⁾	ns

(1) E = EXT_REFCLK1 cycle time in ns.

(2) F = MCU_EXT_REFCLK0 cycle time in ns.

(3) G = AUDIO_EXT_REFCLK0 cycle time in ns.

(4) H = AUDIO_EXT_REFCLK1 cycle time in ns.

TDA4VEN-Q1 TDA4AEN-Q1 Clock Timing
Requirements

Figure 6-14 Clock Timing Requirements

Table 6-20 Clock Switching Characteristics see Figure 6-15

NO.	PARAMETER		MIN	MAX	UNIT
CLK4	t_{c(SYSCLKOUT0)}	Cycle time minimum,SYSCLKOUT0	8		ns
CLK5	t_{w(SYSCLKOUT0H)}	Pulse Duration, SYSCLKOUT0 high	A*0.4⁽¹⁾	A*0.6⁽¹⁾	ns
CLK6	t_{w(SYSCLKOUT0L)}	Pulse Duration, SYSCLKOUT0 low	A*0.4⁽¹⁾	A*0.6⁽¹⁾	ns
CLK4	t_c(OBSCLK0)	Cycle time minimum, OBSCLK0	5		ns
CLK5	t_w(OBSCLK0H)	Pulse Duration, OBSCLK0 high	B*0.45⁽²⁾	B*0.55⁽²⁾	ns
CLK6	t_w(OBSCLK0L)	Pulse Duration, OBSCLK0 low	B*0.45⁽²⁾	B*0.55⁽²⁾	ns
CLK4	t_c(OBSCLK1)	Cycle time minimum, OBSCLK1	5		ns
CLK5	t_w(OBSCLK1H)	Pulse Duration, OBSCLK1 high	F*0.45⁽³⁾	F*0.55⁽³⁾	ns
CLK6	t_w(OBSCLK1L)	Pulse Duration, OBSCLK1 low	F*0.45⁽³⁾	F*0.55⁽³⁾	ns
CLK4	t_c(CLKOUT0)	Cycle time minimum, CLKOUT0	20		ns
CLK5	t_w(CLKOUT0H)	Pulse Duration, CLKOUT0 high	C*0.4⁽⁴⁾	C*0.6⁽⁴⁾	ns
CLK6	t_w(CLKOUT0L)	Pulse Duration, CLKOUT0 low	C*0.4⁽⁴⁾	C*0.6⁽⁴⁾	ns
CLK4	t_{c(MCU_SYSCLKOUT0)}	Cycle time minimum, MCU_SYSCLKOUT0	10		ns
CLK5	t_{w(MCU_SYSCLKOUT0H)}	Pulse Duration, MCU_SYSCLKOUT0 high	E*0.4⁽⁵⁾	E*0.6⁽⁵⁾	ns
CLK6	t_{w(MCU_SYSCLKOUT0L)}	Pulse Duration, MCU_SYSCLKOUT0 low	E*0.4⁽⁵⁾	E*0.6⁽⁵⁾	ns
CLK4	t_{c(MCU_OBSCLK0)}	Cycle time minimum, MCU_OBSCLK0	5		ns
CLK5	t_{w(MCU_OBSCLK0H)}	Pulse Duration, MCU_OBSCLK0 high	D*0.45⁽⁶⁾	D*0.55⁽⁶⁾	ns
CLK6	t_{w(MCU_OBSCLK0L)}	Pulse Duration, MCU_OBSCLK0 low	D*0.45⁽⁶⁾	D*0.55⁽⁶⁾	ns
CLK4	t_{c(WKUP_CLKOUT0)}	Cycle time minimum, WKUP_CLKOUT0	5		ns
CLK5	t_{w(WKUP_CLKOUT0H)}	Pulse Duration, WKUP_CLKOUT0 high	W*0.4⁽⁷⁾	W*0.6⁽⁷⁾	ns
CLK6	t_{w(WKUP_CLKOUT0L)}	Pulse Duration, WKUP_CLKOUT0 low	W*0.4⁽⁷⁾	W*0.6⁽⁷⁾	ns
CLK4	t_{c(AUDIO_EXT_REFCLK0 )}	Cycle time minimum, AUDIO_EXT_REFCLK0 (McASP Clock Source)	20		ns
CLK4	t_{c(AUDIO_EXT_REFCLK0 )}	Cycle time minimum, AUDIO_EXT_REFCLK0 (PLL Clock Source)	10		ns
CLK5	t_{w(AUDIO_EXT_REFCLK0 H)}	Pulse Duration, AUDIO_EXT_REFCLK0 high	G*0.4⁽⁸⁾	G*0.6⁽⁸⁾	ns
CLK6	t_{w(AUDIO_EXT_REFCLK0 L)}	Pulse Duration, AUDIO_EXT_REFCLK0 low	G*0.4⁽⁸⁾	G*0.6⁽⁸⁾	ns
CLK4	t_{c(AUDIO_EXT_REFCLK1 )}	Cycle time minimum, AUDIO_EXT_REFCLK1 (McASP Clock Source)	20		ns
CLK4	t_{c(AUDIO_EXT_REFCLK1 )}	Cycle time minimum, AUDIO_EXT_REFCLK1 (PLL Clock Source)	10		ns
CLK5	t_{w(AUDIO_EXT_REFCLK1 H)}	Pulse Duration, AUDIO_EXT_REFCLK1 high	J*0.4⁽⁹⁾	J*0.6⁽⁹⁾	ns
CLK6	t_{w(AUDIO_EXT_REFCLK1 L)}	Pulse Duration, AUDIO_EXT_REFCLK1 low	J*0.4⁽⁹⁾	J*0.6⁽⁹⁾	ns

(1) A = SYSCLKOUT0 cycle time in ns.

(2) B = OBSCLK0 cycle time in ns.

(3) F = OBSCLK1 cycle time in ns.

(4) C = CLKOUT0 cycle time in ns.

(5) E = MCU_SYSCLKOUT0 cycle time in ns.

(6) D = MCU_OBSCLK0 cycle time in ns.

(7) W = WKUP_CLKOUT0 cycle time in ns.

(8) G = AUDIO_EXT_REFCLK0 cycle time in ns.

(9) J = AUDIO_EXT_REFCLK1 cycle time in ns.

TDA4VEN-Q1 TDA4AEN-Q1 Clock Switching
Characteristics

Figure 6-15 Clock Switching Characteristics