SPRSP62A december 2022 – august 2023 TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Table 7-59, Figure 7-77, Table 7-60, and Figure 7-78 present timing requirements and switching characteristics for MMC0 – Legacy SDR Mode.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
LSDR1 | tsu(cmdV-clkH) | Setup time, MMC0_CMD valid before MMC0_CLK rising edge | 2.5 | ns | |
LSDR2 | th(clkH-cmdV) | Hold time, MMC0_CMD valid after MMC0_CLK rising edge | 6.5 | ns | |
LSDR3 | tsu(dV-clkH) | Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge | 2.5 | ns | |
LSDR4 | th(clkH-dV) | Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge | 6.5 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
fop(clk) | Operating frequency, MMC0_CLK | 25 | MHz | ||
LSDR5 | tc(clk) | Cycle time, MMC0_CLK | 40 | ns | |
LSDR6 | tw(clkH) | Pulse duration, MMC0_CLK high | 18.7 | ns | |
LSDR7 | tw(clkL) | Pulse duration, MMC0_CLK low | 18.7 | ns | |
LSDR8 | td(clkL-cmdV) | Delay time, MMC0_CLK falling edge to MMC0_CMD transition | –3.2 | 3.8 | ns |
LSDR9 | td(clkL-dV) | Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition | –3.2 | 3.8 | ns |