SPRSP62A december   2022  – august 2023 TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
      2.      12
    3. 6.3 Signal Descriptions
      1.      14
      2. 6.3.1  ADC
        1. 6.3.1.1 MCU Domain
          1.        17
          2.        18
          3.        19
      3. 6.3.2  DDRSS
        1. 6.3.2.1 MAIN Domain
          1.        22
          2.        23
      4. 6.3.3  GPIO
        1. 6.3.3.1 MAIN Domain
          1.        26
        2. 6.3.3.2 WKUP Domain
          1.        28
      5. 6.3.4  I2C
        1. 6.3.4.1 MAIN Domain
          1.        31
          2.        32
          3.        33
          4.        34
          5.        35
          6.        36
          7.        37
        2. 6.3.4.2 MCU Domain
          1.        39
          2.        40
        3. 6.3.4.3 WKUP Domain
          1.        42
      6. 6.3.5  I3C
        1. 6.3.5.1 MCU Domain
          1.        45
      7. 6.3.6  MCAN
        1. 6.3.6.1 MAIN Domain
          1.        48
          2.        49
          3.        50
          4.        51
          5.        52
          6.        53
          7.        54
          8.        55
          9.        56
          10.        57
          11.        58
          12.        59
          13.        60
          14.        61
          15.        62
          16.        63
          17.        64
          18.        65
        2. 6.3.6.2 MCU Domain
          1.        67
          2.        68
      8. 6.3.7  MCSPI
        1. 6.3.7.1 MAIN Domain
          1.        71
          2.        72
          3.        73
          4.        74
          5.        75
          6.        76
          7.        77
        2. 6.3.7.2 MCU Domain
          1.        79
          2.        80
      9. 6.3.8  UART
        1. 6.3.8.1 MAIN Domain
          1.        83
          2.        84
          3.        85
          4.        86
          5.        87
          6.        88
          7.        89
          8.        90
          9.        91
          10.        92
        2. 6.3.8.2 MCU Domain
          1.        94
        3. 6.3.8.3 WKUP Domain
          1.        96
      10. 6.3.9  MDIO
        1. 6.3.9.1 MAIN Domain
          1.        99
        2. 6.3.9.2 MCU Domain
          1.        101
      11. 6.3.10 CPSW2G
        1. 6.3.10.1 MAIN Domain
          1.        104
        2. 6.3.10.2 MCU Domain
          1.        106
      12. 6.3.11 ECAP
        1. 6.3.11.1 MAIN Domain
          1.        109
          2.        110
          3.        111
      13. 6.3.12 EQEP
        1. 6.3.12.1 MAIN Domain
          1.        114
          2.        115
          3.        116
      14. 6.3.13 EPWM
        1. 6.3.13.1 MAIN Domain
          1.        119
          2.        120
          3.        121
          4.        122
          5.        123
          6.        124
          7.        125
      15. 6.3.14 USB
        1. 6.3.14.1 MAIN Domain
          1.        128
      16. 6.3.15 Display Port
        1. 6.3.15.1 MAIN Domain
          1.        131
      17. 6.3.16 Hyperlink
        1. 6.3.16.1 MAIN Domain
          1.        134
          2.        135
          3.        136
      18. 6.3.17 PCIE
        1. 6.3.17.1 MAIN Domain
          1.        139
      19. 6.3.18 SERDES
        1. 6.3.18.1 MAIN Domain
          1.        142
      20. 6.3.19 DSI
        1. 6.3.19.1 MAIN Domain
          1.        145
          2.        146
      21. 6.3.20 CSI
        1. 6.3.20.1 MAIN Domain
          1.        149
          2.        150
      22. 6.3.21 MCASP
        1. 6.3.21.1 MAIN Domain
          1.        153
          2.        154
          3.        155
          4.        156
          5.        157
      23. 6.3.22 DMTIMER
        1. 6.3.22.1 MAIN Domain
          1.        160
        2. 6.3.22.2 MCU Domain
          1.        162
      24. 6.3.23 CPTS
        1. 6.3.23.1 MAIN Domain
          1.        165
        2. 6.3.23.2 MCU Domain
          1.        167
      25. 6.3.24 DSS
        1. 6.3.24.1 MAIN Domain
          1.        170
      26. 6.3.25 GPMC
        1. 6.3.25.1 MAIN Domain
          1.        173
      27. 6.3.26 MMC
        1. 6.3.26.1 MAIN Domain
          1.        176
          2.        177
      28. 6.3.27 OSPI
        1. 6.3.27.1 MCU Domain
          1.        180
          2.        181
      29. 6.3.28 Hyperbus
        1. 6.3.28.1 MCU Domain
          1.        184
      30. 6.3.29 Emulation and Debug
        1. 6.3.29.1 MAIN Domain
          1.        187
          2.        188
      31. 6.3.30 System and Miscellaneous
        1. 6.3.30.1 Boot Mode configuration
          1.        191
        2. 6.3.30.2 Clock
          1.        193
          2.        194
        3. 6.3.30.3 System
          1.        196
          2.        197
        4. 6.3.30.4 EFUSE
          1.        199
        5. 6.3.30.5 VMON
          1.        201
      32. 6.3.31 Power
        1.       203
    4. 6.4 Connection for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Power-On-Hour (POH) Limits
    5. 7.5  Operating Performance Points
    6. 7.6  Electrical Characteristics
      1. 7.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 7.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 7.6.3  HFOSC/LFOSC Electrical Characteristics
      4. 7.6.4  eMMCPHY Electrical Characteristics
      5. 7.6.5  SDIO Electrical Characteristics
      6. 7.6.6  CSI2/DSI D-PHY Electrical Characteristics
      7. 7.6.7  ADC12B Electrical Characteristics
      8. 7.6.8  LVCMOS Electrical Characteristics
      9. 7.6.9  USB2PHY Electrical Characteristics
      10. 7.6.10 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
      11. 7.6.11 UFS M-PHY Electrical Characteristics
      12. 7.6.12 eDP/DP AUX-PHY Electrical Characteristics
      13. 7.6.13 DDR0 Electrical Characteristics
    7. 7.7  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.7.2 Hardware Requirements
      3. 7.7.3 Programming Sequence
      4. 7.7.4 Impact to Your Hardware Warranty
    8. 7.8  Thermal Resistance Characteristics
      1. 7.8.1 Thermal Resistance Characteristics for ALZ Package
    9. 7.9  Temperature Sensor Characteristics
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Sequencing
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Combined MCU and Main Domains Power- Up Sequencing
        3. 7.10.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 7.10.2.4 Isolated MCU and Main Domains Power- Up Sequencing
        5. 7.10.2.5 Isolated MCU and Main Domains Power- Down Sequencing
        6. 7.10.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        7. 7.10.2.7 Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        8. 7.10.2.8 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Safety Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input and Output Clocks / Oscillators
          1. 7.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 7.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 7.10.4.1.3.1 Load Capacitance
            2. 7.10.4.1.3.2 Shunt Capacitance
          4. 7.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 7.10.4.1.5 Auxiliary OSC1 Not Used
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
        4. 7.10.4.4 Module and Peripheral Clocks Frequencies
      5. 7.10.5 Peripherals
        1. 7.10.5.1  ATL
          1. 7.10.5.1.1 ATL_PCLK Timing Requirements
          2. 7.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 7.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 7.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 7.10.5.2  CPSW2G
          1. 7.10.5.2.1 CPSW2G MDIO Interface Timings
          2. 7.10.5.2.2 CPSW2G RMII Timings
            1. 7.10.5.2.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 7.10.5.2.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 7.10.5.2.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 7.10.5.2.3 CPSW2G RGMII Timings
            1. 7.10.5.2.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 7.10.5.2.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.10.5.2.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 7.10.5.2.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        3. 7.10.5.3  CSI-2
        4. 7.10.5.4  DDRSS
        5. 7.10.5.5  DSS
        6. 7.10.5.6  eCAP
          1. 7.10.5.6.1 Timing Requirements for eCAP
          2. 7.10.5.6.2 Switching Characteristics for eCAP
        7. 7.10.5.7  EPWM
          1. 7.10.5.7.1 Timing Requirements for eHRPWM
          2. 7.10.5.7.2 Switching Characteristics for eHRPWM
        8. 7.10.5.8  eQEP
          1. 7.10.5.8.1 Timing Requirements for eQEP
          2. 7.10.5.8.2 Switching Characteristics for eQEP
        9. 7.10.5.9  GPIO
          1. 7.10.5.9.1 GPIO Timing Requirements
          2. 7.10.5.9.2 GPIO Switching Characteristics
        10. 7.10.5.10 GPMC
          1. 7.10.5.10.1 GPMC and NOR Flash — Synchronous Mode
            1. 7.10.5.10.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 7.10.5.10.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 7.10.5.10.2 GPMC and NOR Flash — Asynchronous Mode
            1. 7.10.5.10.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.10.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 7.10.5.10.3 GPMC and NAND Flash — Asynchronous Mode
            1. 7.10.5.10.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.10.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 7.10.5.10.4 GPMC0 IOSET
        11. 7.10.5.11 HyperBus
          1. 7.10.5.11.1 Timing Requirements for HyperBus
          2. 7.10.5.11.2 HyperBus 166 MHz Switching Characteristics
          3. 7.10.5.11.3 HyperBus 100 MHz Switching Characteristics
        12. 7.10.5.12 I2C
        13. 7.10.5.13 I3C
        14. 7.10.5.14 MCAN
        15. 7.10.5.15 MCASP
        16. 7.10.5.16 MCSPI
          1. 7.10.5.16.1 MCSPI — Controller Mode
          2. 7.10.5.16.2 MCSPI — Peripheral Mode
        17. 7.10.5.17 MMCSD
          1. 7.10.5.17.1 MMC0 - eMMC Interface
            1. 7.10.5.17.1.1 Legacy SDR Mode
            2. 7.10.5.17.1.2 High Speed SDR Mode
            3. 7.10.5.17.1.3 High Speed DDR Mode
            4. 7.10.5.17.1.4 HS200 Mode
            5. 7.10.5.17.1.5 HS400 Mode
          2. 7.10.5.17.2 MMC1/2 - SD/SDIO Interface
            1. 7.10.5.17.2.1 Default Speed Mode
            2. 7.10.5.17.2.2 High Speed Mode
            3. 7.10.5.17.2.3 UHS–I SDR12 Mode
            4. 7.10.5.17.2.4 UHS–I SDR25 Mode
            5. 7.10.5.17.2.5 UHS–I SDR50 Mode
            6. 7.10.5.17.2.6 UHS–I DDR50 Mode
            7. 7.10.5.17.2.7 UHS–I SDR104 Mode
        18. 7.10.5.18 CPTS
          1. 7.10.5.18.1 CPTS Timing Requirements
          2. 7.10.5.18.2 CPTS Switching Characteristics
        19. 7.10.5.19 OSPI
          1. 7.10.5.19.1 OSPI0 PHY Mode
            1. 7.10.5.19.1.1 OSPI With Data Training
              1. 7.10.5.19.1.1.1 OSPI Switching Characteristics – Data Training
            2. 7.10.5.19.1.2 OSPI Without Data Training
              1. 7.10.5.19.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 7.10.5.19.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 7.10.5.19.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 7.10.5.19.1.2.4 OSPI Switching Characteristics – DDR Mode
          2. 7.10.5.19.2 OSPI0 Tap Mode
            1. 7.10.5.19.2.1 OSPI0 Tap SDR Timing
            2. 7.10.5.19.2.2 OSPI0 Tap DDR Timing
        20. 7.10.5.20 PCIE
        21. 7.10.5.21 Timers
          1. 7.10.5.21.1 Timing Requirements for Timers
          2. 7.10.5.21.2 Switching Characteristics for Timers
        22. 7.10.5.22 UART
          1. 7.10.5.22.1 Timing Requirements for UART
          2. 7.10.5.22.2 UART Switching Characteristics
        23. 7.10.5.23 USB
      6. 7.10.6 Emulation and Debug
        1. 7.10.6.1 Trace
        2. 7.10.6.2 JTAG
          1. 7.10.6.2.1 JTAG Electrical Data and Timing
            1. 7.10.6.2.1.1 JTAG Timing Requirements
            2. 7.10.6.2.1.2 JTAG Switching Characteristics
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply Decoupling and Bulk Capacitors
        1. 8.1.1.1 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG and EMU
      4. 8.1.4 Reset
      5. 8.1.5 Unused Pins
      6. 8.1.6 Hardware Design Guide for JacintoTM 7 Devices
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 LPDDR4 Board Design and Layout Guidelines
      2. 8.2.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 8.2.2.1 No Loopback and Internal Pad Loopback
        2. 8.2.2.2 External Board Loopback
        3. 8.2.2.3 DQS (only available in Octal Flash devices)
      3. 8.2.3 USB VBUS Design Guidelines
      4. 8.2.4 System Power Supply Monitor Design Guidelines using VMON/POK
      5. 8.2.5 High Speed Differential Signal Routing Guidance
      6. 8.2.6 Thermal Solution Guidance
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Trademarks
    5. 9.5 Support Resources
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALZ|770
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.10.5.13 I3C

For more details about features and additional description information on the device Inter-Integrated Circuit, see the corresponding sections within Signal Descriptions, Signal Descriptions and Detailed Description.

Table 7-42, Table 7-43, Figure 7-69, Table 7-44, and Figure 7-70 assume testing over the recommended operating conditions and electrical characteristic conditions.

Table 7-42 I3C Open Drain Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 0.2276 5 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 50 pF
Table 7-43 I3C Open Drain Timing Parameters
NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
D1 tLOW_OD Low Period of SCL Clock Controller 200 ns
tDIG_OD_L tLOW_OD MIN + tFDA_OD MIN ns
D2 tHIGH High Period of SCL Clock Controller 41 ns
tDIG_H tHIGH + tCF ns
D3 tfDA_OD Fall Time of SDA Signal Controller, Target tCF 12 ns
D4 tSU_OD SDA Data Setup Time During Open Drain Mode Controller, Target 3 ns
D5 tCAS Clock After START (S) Condition Controller, ENTAS0 38.4 1000 ns
Controller, ENTAS1 38.4 100000 ns
Controller, ENTAS2 38.4 2000000 ns
Controller, ENTAS3 38.4 50000000 ns
D6 tCBP Clock Before STOP (P) Condition Controller tCAS MIN / 2 ns
D7 tMMOVERLAP Current Controller to Secondary Controller Overlap time during handoff Controller tDIG_OD_Lmin ns
D8 tAVAL Bus Available Condition Controller 1000 ns
D9 tIDLE Bus Idle Condition Controller 1000000 ns
D10 tMMLOCK Time Internal Where New Controller Not Driving SDA Low Controller tAVALmin ns
  1. This is approximately equal to tLOWmin + tDS_ODmin + trDA_ODtyp + tSU_Odmin.
  2. The Controller may use a shorter Low period if the Controller knows that this is safe, when SDA is already above VIH.
  3. Based on tSPIKE, rise and fall times, and interconnect.
  4. This maximum High period may be exceeded when the signals can be safely seen by Legacy I2C Devices, and/or in consideration of the interconnect (for example: a short Bus).
  5. On a Legacy Bus where I2C Devices need to see Start, the tCAS Min value is further constrained.
  6. Targets that do not support the optional ENTASx CCCs shall use the tCAS Max value shown for ENTAS3.
  7. On a Mixed Bus with Fm Legacy I2C Devices, tAVAL is 300ns shorter than the Fm Bus Free Condition time (tBUF).
GUID-9586CB71-3C4A-42A9-BE5C-515C9483AEA7-low.gif Figure 7-69 I3C Open Drain Timing
Table 7-44 I3C Push-Pull Timing Parameters for SDR and HDR-DDR Modes
NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
D1 fSCL SCL Clock Period Controller 80 100000 ns
D2 tLOW SCL Clock Low Period Controller 24 ns
tDIG_L 32 ns
D3 tHIGH_MIXED SCL Clock High Period of Mixed Bus (Mixed Bus Topology Not Supported) Controller 24 ns
tDIG_H_MIXED 32 45 ns
D4 tHIGH SCL Clock High Period Controller 24 ns
tDIG_H 32 ns
D5 tSCO Clock in to Data Out for Target Target 12 ns
D6 tCR SCL Clock Rise Time Controller 150 × 1 / fSCL 60 ns
D7 tCF SCL Clock Fall Time Controller 150 × 1 / fSCL 60 ns
D8 tHD_PP SDA Signal Data Hold in Push Pull Mode Controller tCR + 3 and tCF + 3 ns
Target 0 ns
D9 tSU_PP SDA Signal Data Setup In Push-Pull Mode Controller, Target 3 ns
D10 tCASr Clock After Repeated START (Sr) Controller tCAS MIN ns
D11 tCBSr Clock Before Repeated START (Sr) Controller tCAS MIN / 2 ns
  1. FSCL = 1 / (tDIG_L + tDIG_H)
  2. tDIG_L and tDIG_H are the clock Low and High periods as seen at the receiver end of the I3C Bus using VIL and VIH.
  3. When communicating with an I3C Device on a mixed Bus, the tDIG_H_MIXED period must be constrained to make sure that I2C Devices do not interpret I3C signaling as valid I2C signaling.
  4. As both edges are used, the hold time needs to be satisfied for the respective edges; tCF + 3 for falling edge clocks, and tCR + 3 for rising edge clocks.
  5. Clock Frequency Minimum 0.01 MHz, Maximum 12.5 MHz
GUID-266A0C31-D752-412F-9776-9EA5B12C149F-low.gif Figure 7-70 I3C Push-Pull Timing (SDR and HDR-DDR Modes)