SPRSP62A december 2022 – august 2023 TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
For more details about features and additional description information on the device Inter-Integrated Circuit, see the corresponding sections within Signal Descriptions, Signal Descriptions and Detailed Description.
Table 7-42, Table 7-43, Figure 7-69, Table 7-44, and Figure 7-70 assume testing over the recommended operating conditions and electrical characteristic conditions.
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
INPUT CONDITIONS | ||||
SRI | Input slew rate | 0.2276 | 5 | V/ns |
OUTPUT CONDITIONS | ||||
CL | Output load capacitance | 50 | pF |
NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
D1 | tLOW_OD | Low Period of SCL Clock | Controller | 200 | ns | |
tDIG_OD_L | tLOW_OD MIN + tFDA_OD MIN | ns | ||||
D2 | tHIGH | High Period of SCL Clock | Controller | 41 | ns | |
tDIG_H | tHIGH + tCF | ns | ||||
D3 | tfDA_OD | Fall Time of SDA Signal | Controller, Target | tCF | 12 | ns |
D4 | tSU_OD | SDA Data Setup Time During Open Drain Mode | Controller, Target | 3 | ns | |
D5 | tCAS | Clock After START (S) Condition | Controller, ENTAS0 | 38.4 | 1000 | ns |
Controller, ENTAS1 | 38.4 | 100000 | ns | |||
Controller, ENTAS2 | 38.4 | 2000000 | ns | |||
Controller, ENTAS3 | 38.4 | 50000000 | ns | |||
D6 | tCBP | Clock Before STOP (P) Condition | Controller | tCAS MIN / 2 | ns | |
D7 | tMMOVERLAP | Current Controller to Secondary Controller Overlap time during handoff | Controller | tDIG_OD_Lmin | ns | |
D8 | tAVAL | Bus Available Condition | Controller | 1000 | ns | |
D9 | tIDLE | Bus Idle Condition | Controller | 1000000 | ns | |
D10 | tMMLOCK | Time Internal Where New Controller Not Driving SDA Low | Controller | tAVALmin | ns |
NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
D1 | fSCL | SCL Clock Period | Controller | 80 | 100000 | ns |
D2 | tLOW | SCL Clock Low Period | Controller | 24 | ns | |
tDIG_L | 32 | ns | ||||
D3 | tHIGH_MIXED | SCL Clock High Period of Mixed Bus (Mixed Bus Topology Not Supported) | Controller | 24 | ns | |
tDIG_H_MIXED | 32 | 45 | ns | |||
D4 | tHIGH | SCL Clock High Period | Controller | 24 | ns | |
tDIG_H | 32 | ns | ||||
D5 | tSCO | Clock in to Data Out for Target | Target | 12 | ns | |
D6 | tCR | SCL Clock Rise Time | Controller | 150 × 1 / fSCL | 60 | ns |
D7 | tCF | SCL Clock Fall Time | Controller | 150 × 1 / fSCL | 60 | ns |
D8 | tHD_PP | SDA Signal Data Hold in Push Pull Mode | Controller | tCR + 3 and tCF + 3 | ns | |
Target | 0 | ns | ||||
D9 | tSU_PP | SDA Signal Data Setup In Push-Pull Mode | Controller, Target | 3 | ns | |
D10 | tCASr | Clock After Repeated START (Sr) | Controller | tCAS MIN | ns | |
D11 | tCBSr | Clock Before Repeated START (Sr) | Controller | tCAS MIN / 2 | ns |