SPRSP36K September 2021 – April 2024 TDA4VM , TDA4VM-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
NO. | PARAMETER | MODE(15) | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
133 MHz(20) | ||||||
GNF0 | tw(wenV) | Pulse duration, output write enable GPMC_WEn valid | div_by_1_mode; | A(1) | ns | |
GNF1 | td(csnV-wenV) | Delay time, output chip select GPMC_CSn[i](13) valid to output write enable GPMC_WEn valid | div_by_1_mode; | B(2)-2.55 | B(2)+2.65 | ns |
GNF2 | tw(cleH-wenV) | Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE high to output write enable GPMC_WEn valid | div_by_1_mode; | C(3)-2.55 | C(3)+2.65 | ns |
GNF3 | tw(wenV-dV) | Delay time, output data GPMC_AD[15:0] valid to output write enable GPMC_WEn valid | div_by_1_mode; | D(4)-2.55 | D(4)+2.65 | ns |
GNF4 | tw(wenIV-dIV) | Delay time, output write enable GPMC_WEn invalid to output data GPMC_AD[15:0] invalid | div_by_1_mode; | E(5)-2.55 | E(5)+2.65 | ns |
GNF5 | tw(wenIV-cleIV) | Delay time, output write enable GPMC_WEn invalid to output lower-byte enable and command latch enable GPMC_BE0n_CLE invalid | div_by_1_mode; | F(6)-2.55 | F(6)+2.65 | ns |
GNF6 | tw(wenIV-CSn[i]V) | Delay time, output write enable GPMC_WEn invalid to output chip select GPMC_CSn[i](13) invalid | div_by_1_mode; | G(7)-2.55 | G(7)+2.65 | ns |
GNF7 | tw(aleH-wenV) | Delay time, output address valid and address latch enable GPMC_ADVn_ALE high to output write enable GPMC_WEn valid | div_by_1_mode; | C(3)-2.55 | C(3)+2.65 | ns |
GNF8 | tw(wenIV-aleIV) | Delay time, output write enable GPMC_WEn invalid to output address valid and address latch enable GPMC_ADVn_ALE invalid | div_by_1_mode; | F(6)-2.55 | F(6)+2.65 | ns |
GNF9 | tc(wen) | Cycle time, write | div_by_1_mode; | H(8) | ns | |
GNF10 | td(csnV-oenV) | Delay time, output chip select GPMC_CSn[i](13) valid to output enable GPMC_OEn_REn valid | div_by_1_mode; | I(9)-2.55 | I(9)+2.65 | ns |
GNF13 | tw(oenV) | Pulse duration, output enable GPMC_OEn_REn valid | div_by_1_mode; | K(10) | ns | |
GNF14 | tc(oen) | Cycle time, read | div_by_1_mode; | L(11) | ns | |
GNF15 | tw(oenIV-CSn[i]V) | Delay time, output enable GPMC_OEn_REn invalid to output chip select GPMC_CSn[i](13) invalid | div_by_1_mode; | M(12)-2.55 | M(12)+2.65 | ns |
For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in the device TRM.