SPRSP36K September 2021 – April 2024 TDA4VM , TDA4VM-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Tables and figures provided in this section define timing requirements and switching characteristics for clock signals.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
CLK1 | tc(EXT_REFCLK1) | Cycle time minimum, EXT_REFCLK1 | 10 | ns | |
CLK2 | tw(EXT_REFCLK1H) | Pulse Duration minimum, EXT_REFCLK1 high | E*0.45(1) | E*0.55(1) | ns |
CLK3 | tw(EXT_REFCLK1L) | Pulse Duration minimum, EXT_REFCLK1 low | E*0.45(1) | E*0.55(1) | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
CLK4 | tc(SYSCLKOUT0) | Cycle time minimum,SYSCLKOUT0 | 8 | ns | |
CLK5 | tw(SYSCLKOUT0H) | Pulse Duration minimum, SYSCLKOUT0 high | A*0.4(1) | A*0.6(1) | ns |
CLK6 | tw(SYSCLKOUT0L) | Pulse Duration minimum, SYSCLKOUT0 low | A*0.4(1) | A*0.6(1) | ns |
CLK7 | tc(OBSCLK0) | Cycle time minimum, OBSCLK0 | 5 | ns | |
CLK8 | tw(OBSCLK0H) | Pulse Duration minimum, OBSCLK0 high | B*0.4(2) | B*0.6(2) | ns |
CLK9 | tw(OBSCLK0L) | Pulse Duration minimum,OBSCLK0 low | B*0.4(2) | B*0.6(2) | ns |
CLK10 | tc(CLKOUT0) | Cycle time minimum, CLKOUT0 | 20 | ns | |
CLK11 | tw(CLKOUT0H) | Pulse Duration minimum, CLKOUT0 high | C*0.4(3) | C*0.6(3) | ns |
CLK12 | tw(CLKOUT0L) | Pulse Duration minimum,CLKOUT0 low | C*0.4(3) | C*0.6(3) | ns |