SPRSP36K September   2021  – April 2024 TDA4VM , TDA4VM-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1  ADC
        1. 5.3.1.1 MCU Domain
      2. 5.3.2  DDRSS
        1. 5.3.2.1 MAIN Domain
      3. 5.3.3  GPIO
        1. 5.3.3.1 MAIN Domain
        2. 5.3.3.2 WKUP Domain
      4. 5.3.4  I2C
        1. 5.3.4.1 MAIN Domain
        2. 5.3.4.2 MCU Domain
        3. 5.3.4.3 WKUP Domain
      5. 5.3.5  I3C
        1. 5.3.5.1 MAIN Domain
        2. 5.3.5.2 MCU Domain
      6. 5.3.6  MCAN
        1. 5.3.6.1 MAIN Domain
        2. 5.3.6.2 MCU Domain
      7. 5.3.7  MCSPI
        1. 5.3.7.1 MAIN Domain
        2. 5.3.7.2 MCU Domain
      8. 5.3.8  UART
        1. 5.3.8.1 MAIN Domain
        2. 5.3.8.2 MCU Domain
        3. 5.3.8.3 WKUP Domain
      9. 5.3.9  MDIO
        1. 5.3.9.1 MCU Domain
      10. 5.3.10 CPSW2G
        1. 5.3.10.1 MCU Domain
      11. 5.3.11 CPSW9G
        1. 5.3.11.1 MAIN Domain
      12. 5.3.12 ECAP
        1. 5.3.12.1 MAIN Domain
      13. 5.3.13 EQEP
        1. 5.3.13.1 MAIN Domain
      14. 5.3.14 EHRPWM
        1. 5.3.14.1 MAIN Domain
      15. 5.3.15 USB
        1. 5.3.15.1 MAIN Domain
      16. 5.3.16 SERDES
        1. 5.3.16.1 MAIN Domain
      17. 5.3.17 OSPI
        1. 5.3.17.1 MCU Domain
      18. 5.3.18 Hyperbus
        1. 5.3.18.1 MCU Domain
      19. 5.3.19 GPMC
        1. 5.3.19.1 MAIN Domain
      20. 5.3.20 MMC
        1. 5.3.20.1 MAIN Domain
      21. 5.3.21 CPTS
        1. 5.3.21.1 MCU Domain
        2. 5.3.21.2 MAIN Domain
      22. 5.3.22 UFS
        1. 5.3.22.1 MAIN Domain
      23. 5.3.23 PRU_ICSSG [Currently Not Supported]
        1. 5.3.23.1 MAIN Domain
      24. 5.3.24 MCASP
        1. 5.3.24.1 MAIN Domain
      25. 5.3.25 DSS
        1. 5.3.25.1 MAIN Domain
      26. 5.3.26 DP
        1. 5.3.26.1 MAIN Domain
      27. 5.3.27 Camera Streaming Interface Receiver (CSI_RX_IF) Subsystem
        1. 5.3.27.1 MAIN Domain
      28. 5.3.28 DSI_TX
        1. 5.3.28.1 MAIN Domain
      29. 5.3.29 VPFE
        1. 5.3.29.1 MAIN Domain
      30. 5.3.30 DMTIMER
        1. 5.3.30.1 MAIN Domain
        2. 5.3.30.2 MCU Domain
      31. 5.3.31 Emulation and Debug
        1. 5.3.31.1 MAIN Domain
      32. 5.3.32 System and Miscellaneous
        1. 5.3.32.1 Boot Mode Configuration
          1. 5.3.32.1.1 MAIN Domain
          2. 5.3.32.1.2 MCU Domain
        2. 5.3.32.2 Clock
          1. 5.3.32.2.1 MAIN Domain
          2. 5.3.32.2.2 WKUP Domain
        3. 5.3.32.3 System
          1. 5.3.32.3.1 MAIN Domain
          2. 5.3.32.3.2 WKUP Domain
        4. 5.3.32.4 EFUSE
      33. 5.3.33 Power Supply
    4. 5.4 Pin Multiplexing
    5. 5.5 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Power-On-Hour (POH) Limits
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Operating Performance Points
    6. 6.6 Electrical Characteristics
    7. 6.7 VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.7.2 Hardware Requirements
      3. 6.7.3 Programming Sequence
      4. 6.7.4 Impact to Your Hardware Warranty
    8. 6.8 Thermal Resistance Characteristics
      1. 6.8.1 Thermal Resistance Characteristics for ALF Package
    9. 6.9 Timing and Switching Characteristics
      1. 6.9.1 Timing Parameters and Information
      2. 6.9.2 Power Supply Sequencing
        1. 6.9.2.1 Power Supply Slew Rate Requirement
        2. 6.9.2.2 Combined MCU and Main Domains Power-Up Sequencing
        3. 6.9.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 6.9.2.4 Isolated MCU and Main Domains Power- Up Sequencing
        5. 6.9.2.5 Isolated MCU and Main Domains, Primary Power- Down Sequencing
        6. 6.9.2.6 Entry and Exit of MCU Only State
        7. 6.9.2.7 Entry and Exit of DDR Retention State
      3. 6.9.3 System Timing
        1. 6.9.3.1 Reset Timing
        2. 6.9.3.2 Safety Signal Timing
        3. 6.9.3.3 Clock Timing
      4. 6.9.4 Clock Specifications
        1. 6.9.4.1 Input and Output Clocks / Oscillators
          1. 6.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 6.9.4.1.1.1 Load Capacitance
            2. 6.9.4.1.1.2 Shunt Capacitance
          2. 6.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 6.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 6.9.4.1.3.1 Load Capacitance
            2. 6.9.4.1.3.2 Shunt Capacitance
          4. 6.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 6.9.4.1.5 Auxiliary OSC1 Not Used
          6. 6.9.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
          7. 6.9.4.1.7 WKUP_LFOSC0 Not Used
        2. 6.9.4.2 Output Clocks
        3. 6.9.4.3 PLLs
        4. 6.9.4.4 Module and Peripheral Clocks Frequencies
      5. 6.9.5 Peripherals
        1. 6.9.5.1  ATL
          1. 6.9.5.1.1 ATL_PCLK Timing Requirements
          2. 6.9.5.1.2 ATL_AWS[x] Timing Requirements
          3. 6.9.5.1.3 ATL_BWS[x] Timing Requirements
          4. 6.9.5.1.4 ATCLK[x] Switching Characteristics
        2. 6.9.5.2  VPFE
        3. 6.9.5.3  CPSW2G
          1. 6.9.5.3.1 CPSW2G MDIO Interface Timings
          2. 6.9.5.3.2 CPSW2G RMII Timings
            1. 6.9.5.3.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 6.9.5.3.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 6.9.5.3.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 6.9.5.3.3 CPSW2G RGMII Timings
            1. 6.9.5.3.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 6.9.5.3.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 6.9.5.3.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 6.9.5.3.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        4. 6.9.5.4  CPSW9G
          1. 6.9.5.4.1 CPSW9G MDIO Interface Timings
          2. 6.9.5.4.2 CPSW9G RMII Timings
            1. 6.9.5.4.2.1 RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 6.9.5.4.2.2 RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 6.9.5.4.2.3 RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics – RMII Mode
          3. 6.9.5.4.3 CPSW9G RGMII Timings
            1. 6.9.5.4.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 6.9.5.4.3.2 RGMII[x]_RD[3:0] and RGMII[x]_RCTL Timing Requirements – RGMII Mode
            3. 6.9.5.4.3.3 RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 6.9.5.4.3.4 RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        5. 6.9.5.5  CSI-2
        6. 6.9.5.6  DDRSS
        7. 6.9.5.7  DSS
        8. 6.9.5.8  eCAP
          1. 6.9.5.8.1 Timing Requirements for eCAP
          2. 6.9.5.8.2 Switching Characteristics for eCAP
        9. 6.9.5.9  EPWM
          1. 6.9.5.9.1 Switching Characteristics for eHRPWM
          2. 6.9.5.9.2 Timing Requirements for eHRPWM
        10. 6.9.5.10 eQEP
          1. 6.9.5.10.1 Timing Requirements for eQEP
          2. 6.9.5.10.2 Switching Characteristics for eQEP
        11. 6.9.5.11 GPIO
          1. 6.9.5.11.1 GPIO Timing Requirements
          2. 6.9.5.11.2 GPIO Switching Characteristics
        12. 6.9.5.12 GPMC
          1. 6.9.5.12.1 GPMC and NOR Flash — Synchronous Mode
            1. 6.9.5.12.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 6.9.5.12.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 6.9.5.12.2 GPMC and NOR Flash — Asynchronous Mode
            1. 6.9.5.12.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 6.9.5.12.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 6.9.5.12.3 GPMC and NAND Flash — Asynchronous Mode
            1. 6.9.5.12.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 6.9.5.12.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 6.9.5.12.4 GPMC0 IOSET
        13. 6.9.5.13 HyperBus
          1. 6.9.5.13.1 Timing Requirements for HyperBus
          2. 6.9.5.13.2 HyperBus 166 MHz Switching Characteristics
          3. 6.9.5.13.3 HyperBus 100 MHz Switching Characteristics
        14. 6.9.5.14 I2C
        15. 6.9.5.15 I3C
        16. 6.9.5.16 MCAN
        17. 6.9.5.17 MCASP
        18. 6.9.5.18 MCSPI
          1. 6.9.5.18.1 MCSPI — Master Mode
          2. 6.9.5.18.2 MCSPI — Slave Mode
        19. 6.9.5.19 MMCSD
          1. 6.9.5.19.1 MMC0 - eMMC Interface
            1. 6.9.5.19.1.1 Legacy SDR Mode
            2. 6.9.5.19.1.2 High Speed SDR Mode
            3. 6.9.5.19.1.3 High Speed DDR Mode
            4. 6.9.5.19.1.4 HS200 Mode
          2. 6.9.5.19.2 MMC1/2 - SD/SDIO Interface
            1. 6.9.5.19.2.1 Default Speed Mode
            2. 6.9.5.19.2.2 High Speed Mode
            3. 6.9.5.19.2.3 UHS–I SDR12 Mode
            4. 6.9.5.19.2.4 UHS–I SDR25 Mode
            5. 6.9.5.19.2.5 UHS–I SDR50 Mode
            6. 6.9.5.19.2.6 UHS–I DDR50 Mode
            7. 6.9.5.19.2.7 UHS–I SDR104 Mode
        20. 6.9.5.20 CPTS
          1. 6.9.5.20.1 CPTS Timing Requirements
          2. 6.9.5.20.2 CPTS Switching Characteristics
        21. 6.9.5.21 OSPI
          1. 6.9.5.21.1 OSPI PHY Mode
            1. 6.9.5.21.1.1 OSPI With Data Training
              1. 6.9.5.21.1.1.1 OSPI Switching Characteristics – Data Training
            2. 6.9.5.21.1.2 OSPI Without Data Training
              1. 6.9.5.21.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 6.9.5.21.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 6.9.5.21.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 6.9.5.21.1.2.4 OSPI Switching Characteristics – DDR Mode
          2. 6.9.5.21.2 OSPI Tap Mode
            1. 6.9.5.21.2.1 OSPI Tap SDR Timing
            2. 6.9.5.21.2.2 OSPI Tap DDR Timing
        22. 6.9.5.22 PCIE
        23. 6.9.5.23 Timers
          1. 6.9.5.23.1 Timing Requirements for Timers
          2. 6.9.5.23.2 Switching Characteristics for Timers
        24. 6.9.5.24 UART
          1. 6.9.5.24.1 Timing Requirements for UART
          2. 6.9.5.24.2 UART Switching Characteristics
        25. 6.9.5.25 USB
      6. 6.9.6 Emulation and Debug
        1. 6.9.6.1 Trace
        2. 6.9.6.2 JTAG
          1. 6.9.6.2.1 JTAG Electrical Data and Timing
            1. 6.9.6.2.1.1 JTAG Timing Requirements
            2. 6.9.6.2.1.2 JTAG Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A72
      2. 7.2.2 Arm Cortex-R5F
      3. 7.2.3 DSP C71x
      4. 7.2.4 DSP C66x
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 GPU
      2. 7.3.2 VPAC
      3. 7.3.3 DMPAC
      4. 7.3.4 D5520MP2
      5. 7.3.5 VXE384MP2
    4. 7.4 Other Subsystems
      1. 7.4.1 MSMC
      2. 7.4.2 NAVSS
        1. 7.4.2.1 NAVSS0
        2. 7.4.2.2 MCU_NAVSS
      3. 7.4.3 PDMA Controller
      4. 7.4.4 Power Supply
      5. 7.4.5 Peripherals
        1. 7.4.5.1  ADC
        2. 7.4.5.2  ATL
        3. 7.4.5.3  CSI
          1. 7.4.5.3.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
          2. 7.4.5.3.2 Camera Streaming Interface Transmitter (CSI_TX_IF)
        4. 7.4.5.4  CPSW2G
        5. 7.4.5.5  CPSW9G
        6. 7.4.5.6  DCC
        7. 7.4.5.7  DDRSS
        8. 7.4.5.8  DSS
          1. 7.4.5.8.1 DSI
          2. 7.4.5.8.2 eDP
        9. 7.4.5.9  VPFE
        10. 7.4.5.10 eCAP
        11. 7.4.5.11 EPWM
        12. 7.4.5.12 ELM
        13. 7.4.5.13 ESM
        14. 7.4.5.14 eQEP
        15. 7.4.5.15 GPIO
        16. 7.4.5.16 GPMC
        17. 7.4.5.17 Hyperbus
        18. 7.4.5.18 I2C
        19. 7.4.5.19 I3C
        20. 7.4.5.20 MCAN
        21. 7.4.5.21 MCASP
        22. 7.4.5.22 MCRC Controller
        23. 7.4.5.23 MCSPI
        24. 7.4.5.24 MMC/SD
        25. 7.4.5.25 OSPI
        26. 7.4.5.26 PCIE
        27. 7.4.5.27 SerDes
        28. 7.4.5.28 WWDT
        29. 7.4.5.29 Timers
        30. 7.4.5.30 UART
        31. 7.4.5.31 USB
        32. 7.4.5.32 UFS
  9. 8 Applications and Implementation
    1. 8.1 Power Supply Mapping
    2. 8.2 Device Connection and Layout Fundamentals
      1. 8.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 8.2.1.1 Power Distribution Network Implementation Guidance
      2. 8.2.2 External Oscillator
      3. 8.2.3 JTAG and EMU
      4. 8.2.4 Reset
      5. 8.2.5 Unused Pins
      6. 8.2.6 Hardware Design Guide for JacintoTM 7 Devices
    3. 8.3 Peripheral- and Interface-Specific Design Information
      1. 8.3.1 LPDDR4 Board Design and Layout Guidelines
      2. 8.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 8.3.2.1 No Loopback and Internal Pad Loopback
        2. 8.3.2.2 External Board Loopback
        3. 8.3.2.3 DQS (only available in Octal Flash devices)
      3. 8.3.3 SERDES REFCLK Design Guidelines
      4. 8.3.4 USB VBUS Design Guidelines
      5. 8.3.5 System Power Supply Monitor Design Guidelines
      6. 8.3.6 High Speed Differential Signal Routing Guidance
      7. 8.3.7 Thermal Solution Guidance
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALF|827
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics

Note:

The interfaces or signals described in Table 6-2through Table 6-9 correspond to the interfaces or signals available in multiplexing mode 0 (Primary Function).

All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC electrical characteristics are specified for the different multiplexing modes (Functions).

Table 6-2 I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics Over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BALL NAMES in Mode 0: WKUP_I2C0_SDA, WKUP_I2C0_SCL, MCU_I2C0_SDA, MCU_I2C0_SCL, I2C0_SDA, I2C0_SCL, I2C1_SDA, I2C1_SCL, EXTINTN
BALL NUMBERS:H24 / J25 / H25 / J26 / AA5 / AC5 / AA6 / Y6 / AC18 H24/ J25 / H25 / J26 / AA5 / AC5 / AA6 / Y6 / AC18
1.8-V MODE
VIL Input low-level threshold 0.3 × VDDSHV(1) V
VILSS Input low-level threshold steady state 0.3 × VDDSHV(1) V
VIH Input high-level threshold 0.7 × VDDSHV(1) V
VIHSS Input high-level threshold steady state 0.7 × VDDSHV(1) V
VHYS Input Hysteresis Voltage 0.1 × VDDSHV(1) mV
IIN Input Leakage Current VI = 1.8 V or 0 V ±10 µA
VOL Output low-level voltage 0.2 × VDDSHV(1) V
IOL(2) Low Level Output Current VOL(MAX) 6 mA
SRI(4) Input Slew Rate 18f(3)
or
1.8E+6		 V/s
3.3-V MODE(5)
VIL Input low-level threshold 0.3 × VDDSHV(1) V
VILSS Input low-level threshold steady state 0.25 × VDDSHV(1) V
VIH Input high-level threshold 0.7 × VDDSHV(1) V
VIHSS Input high-level threshold steady state 0.7 × VDDSHV(1) V
VHYS Input Hysteresis Voltage 0.05 × VDDSHV(1) mV
IIN Input Leakage Current VI = 3.3 V or 0 V ±10 µA
VOL Output low-level voltage 0.4(1) V
IOL(2) Low Level Output Current VOL(MAX) 6 mA
SRI(4) Input Slew Rate 33f(3)
or
3.3E+6		 8E + 7 V/s
(1) VDDSHV stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Section 5.2, Pin Attributes, POWER column.
(2) The IOL parameter defines the minimum Low Level Output Current for which the device is able to maintain the specified VOL value. The value defined by this parameter should be considered the maximum current available to a system implementation which needs to maintain the specified VOL value for attached components.
(3) f = toggle frequency of the input signal in Hz.
(4) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching Characteristics sections. Select the MIN parameter which results in the largest value.
(5) I2C Hs-mode is not supported, when operating the IO in 3.3-V mode.
Table 6-3 Fail-Safe Reset (FS Reset) Electrical Characteristics Over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BALL NAMES in Mode 0: MCU_PORz, PORz
BALL NUMBERS:H23 / J24
VIL Input low-level threshold 0.3 × VDDSHV(1) V
VILSS Input low-level threshold steady state 0.3 × VDDSHV(1) V
VIH Input high-level threshold 0.7 × VDDSHV(1) V
VIHSS Input high-level threshold steady state 0.7 × VDDSHV(1) V
VHYS Input Hysteresis Voltage 200 mV
IIN Input Leakage Current VI = 1.8 V or 0 V ±10 µA
(1) VDDSHV stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Section 5.2, Pin Attributes, POWER column.
Table 6-4 HFOSC/LFOSC Electrical Characteristics Over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HIGH FREQUENCY OSCILLATOR
BALL NAMES: WKUP_OSC0_XO, WKUP_OSC0_XI, OSC1_XO, OSC1_XI
BALL NUMBERS:M27 / M29 / P27 / P29
VIH Input high-level threshold 0.65 × VDDSHV(1) V
VIL Input low-level threshold 0.35 × VDDSHV(1) V
VHYS Input Hysteresis Voltage 49 mV
LOW FREQUENCY OSCILLATOR
BALL NAMES: WKUP_LFOSC0_XO, WKUP_LFOSC0_XI
BALL NUMBERS:N26 / N28
VIH Input high-level threshold 0.65 × VDDA_WKUP(1) V
VIL Input low-level threshold 0.35 × VDDA_WKUP(1) V
VHYS Input Hysteresis Voltage Active Mode 85 mV
Bypass Mode 324 mV
(1) VDDSHV stands for corresponding power supply. For WKUP_OSC0, the corresponding power supply is VDDA_WKUP. For OSC1_XI, the corresponding power supply is VDDS_OSC1.
Table 6-5 eMMCPHY Electrical Characteristics Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
BALL NAMES in Mode 0: MMC0_DAT[7:0], MMC0_CALPAD, MMC0_CMD, MMC0_DS, MMC0_CLK
BALL NUMBERS:AG2 / AH1 / AG3 / AF4 / AE5 / AF3 / AG1 / AF2 / AE1 / AE3 / AE4 / AF1
VIL Input low-level threshold 0.35 × VDDSHV(1) V
VILSS Input low-level threshold steady state 0.20 V
VIH Input high-level threshold 0.65 × VDDSHV(1) V
VIHSS Input high-level threshold steady state 1.4 V
IIN Input Leakage Current VI = 1.8 V or 0 V ±10 µA
IOZ Tri-state Output Leakage Current VO = 1.8 V or 0 V ±10 µA
RPU Pull-up Resistor 15 20 25 kΩ
RPD Pull-down Resistor 15 20 25 kΩ
VOL Output low-level voltage 0.30 V
VOH Output high-level voltage VDDSHV - 0.30(1) V
IOL Low Level Output Current VOL(MAX) 2 mA
IOH High Level Output Current VOH(MAX) 2 mA
SRI Input Slew Rate 5E + 8 V/s
(1) VDDSHV stands for corresponding power supply (vddshv8). For more information on the power supply name and the corresponding ball, see Section 5.2, Pin Attributes, POWER column.
Table 6-6 SDIO Electrical Characteristics Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
BALL NAMES in Mode 0: MMC1_CLK, MMC1_CMD, MMC1_DAT[3:0], MMC2_CLK, MMC2_CMD, MMC2_DAT[3:0]
BALL NUMBERS:P25 / R29 / R24 / P24 / R25 / R26 / T26 / T25 / T24 / T27 / T29 / T28
1.8-V MODE
VIL Input low-level threshold 0.58 V
VILSS Input low-level threshold steady state 0.58 V
VIH Input high-level threshold 1.27 V
VIHSS Input high-level threshold steady state 1.7 V
VHYS Input Hysteresis Voltage 150 mV
IIN Input Leakage Current VI = 1.8 V or 0 V ±10 µA
RPU Pull-up Resistor 40 50 60 kΩ
RPD Pull-down Resistor 40 50 60 kΩ
VOL Output low-level voltage 0.45 V
VOH Output high-level voltage VDDSHV- 0.45(1) V
IOL Low Level Output Current VOL(MAX) 4 mA
IOH High Level Output Current VOH(MAX) 4 mA
SRI(3) Input Slew Rate 18f(2)
or
1.8E+6		 V/s
3.3-V Mode
VIL Input low-level threshold 0.25 × VDDSHV(1) V
VILSS Input low-level threshold steady state 0.15 × VDDSHV(1) V
VIH Input high-level threshold 0.625 × VDDSHV(1) V
VIHSS Input high-level threshold steady state 0.625 × VDDSHV(1) V
VHYS Input Hysteresis Voltage 150 mV
IIN Input Leakage Current VI = 1.8 V or 0 V ±10 µA
RPU Pull-up Resistor 40 50 60 kΩ
RPD Pull-down Resistor 40 50 60 kΩ
VOL Output low-level voltage 0.125 × VDDSHV(1) V
VOH Output high-level voltage 0.75 × VDDSHV(1) V
IOL Low Level Output Current VOL(MAX) 6 mA
IOH High Level Output Current VOH(MAX) 10 mA
SRI(3) Input Slew Rate 33f(2)
or
3.3E+6		 V/s
(1) VDDSHV stands for corresponding power supply (vddshv8). For more information on the power supply name and the corresponding ball, see Section 5.2, Pin Attributes, POWER column.
(2) f = toggle frequency of the input signal in Hz.
(3) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching Characteristics sections. Select the MIN parameter which results in the largest value.

CSI-2/DSI D-PHY Electrical Characteristics

Note:

CSI-2/DSI (D-PHY) interfaces are compliant with MIPI D-PHY specifications v1.2 dated August 1, 2014, including ECNs and Errata as applicable.

Table 6-7 ADC12B Electrical Characteristics Over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BALL NAMES in Mode 0: MCU_ADC0_AIN[7:0], MCU_ADC1_AIN[7:0]
BALL NUMBERS:K24 / K25 / K26 / K27 / K28 / K29 / L24 / L25 / L26 / L27 / L28 / L29 / M24 / M25 / N23 / N24
Analog Input
VMCU_ADC0/1_AIN[7:0] Full-scale Input Range VSS VDDA_ADC0/1 V
DNL Differential Non-Linearity -1 0.5 4 LSB
INL Integral Non-Linearity ±1 ±4 LSB
LSBGAIN-ERROR Gain Error ±2 LSB
LSBOFFSET-ERROR Offset Error ±2 LSB
CIN Input Sampling Capacitance 5.5 pF
SNR Signal-to-Noise Ratio Input Signal: 200 kHz sine wave at -0.5 dB Full Scale 70 dB
THD Total Harmonic Distortion Input Signal: 200 kHz sine wave at -0.5 dB Full Scale 73 dB
SFDR Spurious Free Dynamic Range Input Signal: 200 kHz sine wave at -0.5 dB Full Scale 76 dB
SNR(PLUS) Signal-to-Noise Plus Distortion Input Signal: 200 kHz sine wave at -0.5 dB Full Scale 69 dB
RMCU_ADC0/1_AIN[0:7] Input Impedance of MCU_ADC0/1_AIN[7:0] f = input frequency [1/((65.97 × 10–-12) × fSMPL_CLK)] Ω
IIN Input Leakage MCU_ADC0/1_AIN[7:0] = VSS -10 μA
MCU_ADC0/1_AIN[7:0] = VDDA_ADC0/1 24 μA
Sampling Dynamics
FSMPL_CLK SMPL_CLK Frequency 60 MHz
tC Conversion Time 13 ADC0/1 SMPL_CLK Cycles
tACQ Acquisition time 2 257 ADC0/1 SMPL_CLK Cycles
TR Sampling Rate ADC0/1 SMPL_CLK = 60 MHz 4 MSPS
CCISO Channel to Channel Isolation 100 dB
General Purpose Input Mode(1)
VIL Input low-level threshold 0.35 × VDDA_ADC0/1 V
VILSS Input high-level threshold steady state 0.35 × VDDA_ADC0/1 V
VIH Input high-level threshold 0.65 × VDDA_ADC0/1 V
VIHSS Input high-level threshold steady state 0.65 × VDDA_ADC0/1 V
VHYS Input Hysteresis Voltage 200 mV
IIN Input Leakage Current VI = 1.8 V or 0 V 6 µA
(1) MCU_ADC0/1 can be configured to operate in General Purpose Input mode, where all MCU_ADC0/1_AIN[7:0] inputs are globally enabled to operate as digital inputs via the ADC0/1_CTRL register (gpi_mode_en = 1).
Table 6-8 MLB LVCMOS Electrical Characteristics Only GPIO mode supported. Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BALL NAMES in Mode 0: MLB0_MLBSN, MLB0_MLBDP, MLB0_MLBSP, MLB0_MLBCP, MLB0_MLBDN, MLB0_MLBCN
BALL NUMBERS:AC1 / AC3 / AD1 / AD2 / AD3 / AE2
VIL Input Low Voltage 0.3 × VDD(1) V
VILSS Input Low Voltage Steady State 0.3 × VDD(1) V
VIH Input High Voltage 0.7 × VDD(1) V
VIHSS Input High Voltage Steady State 0.75 × VDD(1) V
VHYS Input Hysteresis Voltage 80 mV
IIN Input Leakage Current VI = 1.8 V or 0 V ±10 µA
RPD Pull-down Resistor 20 53 130 kΩ
VOL Output Low Voltage 0.2 V
VOH Output High Voltage VDD(1) - 0.2 V
IOL Low Level Output Current VOL(MAX) 6 mA
IOH High Level Output Current VOH(MIN) 6 mA
SRI Input Slew Rate(2) fop > 100 MHz 1 V/ns
fop < 1 MHz 10 V/ns
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Section 5.2, Pin Attributes, POWER column.
(2) Slew rate may be further limited, reference Section 6.9 for actual slew rate during operation.
Table 6-9 LVCMOS Electrical Characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER(1) TEST CONDITIONS MIN TYP MAX UNIT
BALL NAMES: ALL other IOs
BALL NUMBERS: ALL other IOs
1.8-V MODE
VIL Input Low Voltage 0.35 × VDD(1) V
VILSS Input Low Voltage Steady State 0.3 × VDD(1) V
VIH Input High Voltage 0.65 × VDD(1) V
VIHSS Input High Voltage Steady State 0.85 × VDD(1) V
VHYS Input Hysteresis Voltage 150 mV
IIN Input Leakage Current. VI = 1.8 V or 0 V ±10 µA
RPU Pull-up Resistor 15 22 30 kΩ
RPD Pull-down Resistor 15 22 30 kΩ
VOL Output Low Voltage 0.45 V
VOH Output High Voltage VDD(1) - 0.45 V
IOL(2) Low Level Output Current VOL(MAX) 3 mA
IOH(2) High Level Output Current VOH(MIN) 3 mA
SRI(4) Input Slew Rate 18f(3)
or
1.8E+6		 V/s
3.3-V MODE
VIL Input Low Voltage 0.8 V
VILSS Input Low Voltage Steady State 0.6 V
VIH Input High Voltage 2.0 V
VIHSS Input High Voltage Steady State 2.0 V
VHYS Input Hysteresis Voltage 150 mV
IIN Input Leakage Current. VI = 3.3 V or 0 V ±10 µA
RPD Pull-down Resistor 15 22 30 kΩ
VOL Output Low Voltage 0.4 V
VOH Output High Voltage 2.4 V
IOL(2) Low Level Output Current VOL(MAX) 5 mA
IOH(2) High Level Output Current VOH(MIN) 6 mA
SRI(4) Input Slew Rate 33f(3)
or
3.3E+6		 V/s
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Section 5.2, Pin Attributes, POWER column.
(2) The IOL and IOH parameters define the minimum Low Level Output Current and High Level Output Current for which the device is able to maintain the specified VOL and VOH values. Values defined by these parameters should be considered the maximum current available to a system implementation which needs to maintain the specified VOL and VOH values for attached components.
(3) f = toggle frequency of the input signal in Hz.
(4) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching Characteristics sections. Select the MIN parameter which results in the largest value.

USB2PHY Electrical Characteristics

Note:

USB0 and USB1 Electrical Characteristics are compliant with Universal Serial Bus Revision 2.0 Specification dated April 27, 2000 including ECNs and Errata as applicable.

 

SerDes 4-L-PHY/2-L-PHY Electrical Characteristics

Note:

The PCIe interfaces are compliant with the electrical parameters specified in PCI Express® Base Specification Revision 4.0, September 27, 2017.

This Device imposes an additional limit on SERDES REFCLK when used in Input mode with internal termination enabled, as described by parameter VREFCLK_TERM in Table 6-10, 4-L-PHY SERDES REFCLK Electrical Characteristics. Internal termination is enabled by default and must be disabled before applying a reference clock signal that exceeds the limits defined by VREFCLK_TERM. External termination should always be enabled on the source side.

Table 6-10 4-L-PHY SERDES REFCLK Electrical Characteristics Only applies when internal termination is enabled. Over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
BALL NAMES in Mode 0: SERDES4_REFCLK_P, SERDES4_REFCLK_N
BALL NUMBERS:E8 / E7
VREFCLK_TERM Single ended voltage threshold at the reference clock pin when internal termination is enabled 400 mV
RTERM Internal termination 40 50 62.5 Ω
Note:

The SerDes USB interfaces are compliant with the USB3.1 SuperSpeed Transmitter and Receiver Normative Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision 1.0 , July 26, 2013.

Note:

The SGMII interfaces electrical characteristics are compliant with 1000BASE-KX per IEEE802.3 Clause 70.

Note:

The SGMII 2.5G / XAUI interfaces electrical characteristics are compliant with IEEE802.3 Clause 47.

Note:

The QSGMII interface electrical characteristics are compliant with QSGMII Specification revision 1.2.

This Device imposes an additional limit on the 2-L-PHY SERDES REFCLK, as described by parameters VIDTH and VIDTL in Table 6-11, 2-L-PHY SERDES REFCLK Electrical Characteristics.

Table 6-11 2-L-PHY SERDES REFCLK Electrical Characteristics Only applies when internal termination is enabled. Over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
BALL NAMES in Mode 0: PCIE_REFCLK[3:0]P, PCIE_REFCLK[3:0]N
BALL NUMBERS:AE9 / AD10 / AE11 / AD12 / AE14 / AD15 / AE17 / AD16
VIDTH Input Differential high-level threshold 200 mV
VIDTL Input Differential low-level threshold –200 mV

UFS M-PHY Electrical Characteristics

Note:

The UFS interface electrical characteristics are compliant with MIPI M-PHY Specification v3.1, February 17, 2014.

eDP/DP AUX-PHY Electrical Characteristics

Note:

The DP interface electrical characteristics are compliant with the VESA DisplayPort (DP) Standard v 1.4 February 23, 2016.

Note:

The eDP interface electrical characteristics are compliant with the VESA Embedded DisplayPort (eDP) Standard v1.4b October 23, 2015.

DDR0 Electrical Characteristics

Note:

The DDR interface is compatible with JESD209-4B standard compliant LPDDR4 SDRAM devices.