SPRSP36K September   2021  – April 2024 TDA4VM , TDA4VM-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1  ADC
        1. 5.3.1.1 MCU Domain
      2. 5.3.2  DDRSS
        1. 5.3.2.1 MAIN Domain
      3. 5.3.3  GPIO
        1. 5.3.3.1 MAIN Domain
        2. 5.3.3.2 WKUP Domain
      4. 5.3.4  I2C
        1. 5.3.4.1 MAIN Domain
        2. 5.3.4.2 MCU Domain
        3. 5.3.4.3 WKUP Domain
      5. 5.3.5  I3C
        1. 5.3.5.1 MAIN Domain
        2. 5.3.5.2 MCU Domain
      6. 5.3.6  MCAN
        1. 5.3.6.1 MAIN Domain
        2. 5.3.6.2 MCU Domain
      7. 5.3.7  MCSPI
        1. 5.3.7.1 MAIN Domain
        2. 5.3.7.2 MCU Domain
      8. 5.3.8  UART
        1. 5.3.8.1 MAIN Domain
        2. 5.3.8.2 MCU Domain
        3. 5.3.8.3 WKUP Domain
      9. 5.3.9  MDIO
        1. 5.3.9.1 MCU Domain
      10. 5.3.10 CPSW2G
        1. 5.3.10.1 MCU Domain
      11. 5.3.11 CPSW9G
        1. 5.3.11.1 MAIN Domain
      12. 5.3.12 ECAP
        1. 5.3.12.1 MAIN Domain
      13. 5.3.13 EQEP
        1. 5.3.13.1 MAIN Domain
      14. 5.3.14 EHRPWM
        1. 5.3.14.1 MAIN Domain
      15. 5.3.15 USB
        1. 5.3.15.1 MAIN Domain
      16. 5.3.16 SERDES
        1. 5.3.16.1 MAIN Domain
      17. 5.3.17 OSPI
        1. 5.3.17.1 MCU Domain
      18. 5.3.18 Hyperbus
        1. 5.3.18.1 MCU Domain
      19. 5.3.19 GPMC
        1. 5.3.19.1 MAIN Domain
      20. 5.3.20 MMC
        1. 5.3.20.1 MAIN Domain
      21. 5.3.21 CPTS
        1. 5.3.21.1 MCU Domain
        2. 5.3.21.2 MAIN Domain
      22. 5.3.22 UFS
        1. 5.3.22.1 MAIN Domain
      23. 5.3.23 PRU_ICSSG [Currently Not Supported]
        1. 5.3.23.1 MAIN Domain
      24. 5.3.24 MCASP
        1. 5.3.24.1 MAIN Domain
      25. 5.3.25 DSS
        1. 5.3.25.1 MAIN Domain
      26. 5.3.26 DP
        1. 5.3.26.1 MAIN Domain
      27. 5.3.27 Camera Streaming Interface Receiver (CSI_RX_IF) Subsystem
        1. 5.3.27.1 MAIN Domain
      28. 5.3.28 DSI_TX
        1. 5.3.28.1 MAIN Domain
      29. 5.3.29 VPFE
        1. 5.3.29.1 MAIN Domain
      30. 5.3.30 DMTIMER
        1. 5.3.30.1 MAIN Domain
        2. 5.3.30.2 MCU Domain
      31. 5.3.31 Emulation and Debug
        1. 5.3.31.1 MAIN Domain
      32. 5.3.32 System and Miscellaneous
        1. 5.3.32.1 Boot Mode Configuration
          1. 5.3.32.1.1 MAIN Domain
          2. 5.3.32.1.2 MCU Domain
        2. 5.3.32.2 Clock
          1. 5.3.32.2.1 MAIN Domain
          2. 5.3.32.2.2 WKUP Domain
        3. 5.3.32.3 System
          1. 5.3.32.3.1 MAIN Domain
          2. 5.3.32.3.2 WKUP Domain
        4. 5.3.32.4 EFUSE
      33. 5.3.33 Power Supply
    4. 5.4 Pin Multiplexing
    5. 5.5 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Power-On-Hour (POH) Limits
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Operating Performance Points
    6. 6.6 Electrical Characteristics
    7. 6.7 VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.7.2 Hardware Requirements
      3. 6.7.3 Programming Sequence
      4. 6.7.4 Impact to Your Hardware Warranty
    8. 6.8 Thermal Resistance Characteristics
      1. 6.8.1 Thermal Resistance Characteristics for ALF Package
    9. 6.9 Timing and Switching Characteristics
      1. 6.9.1 Timing Parameters and Information
      2. 6.9.2 Power Supply Sequencing
        1. 6.9.2.1 Power Supply Slew Rate Requirement
        2. 6.9.2.2 Combined MCU and Main Domains Power-Up Sequencing
        3. 6.9.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 6.9.2.4 Isolated MCU and Main Domains Power- Up Sequencing
        5. 6.9.2.5 Isolated MCU and Main Domains, Primary Power- Down Sequencing
        6. 6.9.2.6 Entry and Exit of MCU Only State
        7. 6.9.2.7 Entry and Exit of DDR Retention State
      3. 6.9.3 System Timing
        1. 6.9.3.1 Reset Timing
        2. 6.9.3.2 Safety Signal Timing
        3. 6.9.3.3 Clock Timing
      4. 6.9.4 Clock Specifications
        1. 6.9.4.1 Input and Output Clocks / Oscillators
          1. 6.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 6.9.4.1.1.1 Load Capacitance
            2. 6.9.4.1.1.2 Shunt Capacitance
          2. 6.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 6.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 6.9.4.1.3.1 Load Capacitance
            2. 6.9.4.1.3.2 Shunt Capacitance
          4. 6.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 6.9.4.1.5 Auxiliary OSC1 Not Used
          6. 6.9.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
          7. 6.9.4.1.7 WKUP_LFOSC0 Not Used
        2. 6.9.4.2 Output Clocks
        3. 6.9.4.3 PLLs
        4. 6.9.4.4 Module and Peripheral Clocks Frequencies
      5. 6.9.5 Peripherals
        1. 6.9.5.1  ATL
          1. 6.9.5.1.1 ATL_PCLK Timing Requirements
          2. 6.9.5.1.2 ATL_AWS[x] Timing Requirements
          3. 6.9.5.1.3 ATL_BWS[x] Timing Requirements
          4. 6.9.5.1.4 ATCLK[x] Switching Characteristics
        2. 6.9.5.2  VPFE
        3. 6.9.5.3  CPSW2G
          1. 6.9.5.3.1 CPSW2G MDIO Interface Timings
          2. 6.9.5.3.2 CPSW2G RMII Timings
            1. 6.9.5.3.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 6.9.5.3.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 6.9.5.3.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 6.9.5.3.3 CPSW2G RGMII Timings
            1. 6.9.5.3.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 6.9.5.3.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 6.9.5.3.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 6.9.5.3.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        4. 6.9.5.4  CPSW9G
          1. 6.9.5.4.1 CPSW9G MDIO Interface Timings
          2. 6.9.5.4.2 CPSW9G RMII Timings
            1. 6.9.5.4.2.1 RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 6.9.5.4.2.2 RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 6.9.5.4.2.3 RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics – RMII Mode
          3. 6.9.5.4.3 CPSW9G RGMII Timings
            1. 6.9.5.4.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 6.9.5.4.3.2 RGMII[x]_RD[3:0] and RGMII[x]_RCTL Timing Requirements – RGMII Mode
            3. 6.9.5.4.3.3 RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 6.9.5.4.3.4 RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        5. 6.9.5.5  CSI-2
        6. 6.9.5.6  DDRSS
        7. 6.9.5.7  DSS
        8. 6.9.5.8  eCAP
          1. 6.9.5.8.1 Timing Requirements for eCAP
          2. 6.9.5.8.2 Switching Characteristics for eCAP
        9. 6.9.5.9  EPWM
          1. 6.9.5.9.1 Switching Characteristics for eHRPWM
          2. 6.9.5.9.2 Timing Requirements for eHRPWM
        10. 6.9.5.10 eQEP
          1. 6.9.5.10.1 Timing Requirements for eQEP
          2. 6.9.5.10.2 Switching Characteristics for eQEP
        11. 6.9.5.11 GPIO
          1. 6.9.5.11.1 GPIO Timing Requirements
          2. 6.9.5.11.2 GPIO Switching Characteristics
        12. 6.9.5.12 GPMC
          1. 6.9.5.12.1 GPMC and NOR Flash — Synchronous Mode
            1. 6.9.5.12.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 6.9.5.12.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 6.9.5.12.2 GPMC and NOR Flash — Asynchronous Mode
            1. 6.9.5.12.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 6.9.5.12.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 6.9.5.12.3 GPMC and NAND Flash — Asynchronous Mode
            1. 6.9.5.12.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 6.9.5.12.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 6.9.5.12.4 GPMC0 IOSET
        13. 6.9.5.13 HyperBus
          1. 6.9.5.13.1 Timing Requirements for HyperBus
          2. 6.9.5.13.2 HyperBus 166 MHz Switching Characteristics
          3. 6.9.5.13.3 HyperBus 100 MHz Switching Characteristics
        14. 6.9.5.14 I2C
        15. 6.9.5.15 I3C
        16. 6.9.5.16 MCAN
        17. 6.9.5.17 MCASP
        18. 6.9.5.18 MCSPI
          1. 6.9.5.18.1 MCSPI — Master Mode
          2. 6.9.5.18.2 MCSPI — Slave Mode
        19. 6.9.5.19 MMCSD
          1. 6.9.5.19.1 MMC0 - eMMC Interface
            1. 6.9.5.19.1.1 Legacy SDR Mode
            2. 6.9.5.19.1.2 High Speed SDR Mode
            3. 6.9.5.19.1.3 High Speed DDR Mode
            4. 6.9.5.19.1.4 HS200 Mode
          2. 6.9.5.19.2 MMC1/2 - SD/SDIO Interface
            1. 6.9.5.19.2.1 Default Speed Mode
            2. 6.9.5.19.2.2 High Speed Mode
            3. 6.9.5.19.2.3 UHS–I SDR12 Mode
            4. 6.9.5.19.2.4 UHS–I SDR25 Mode
            5. 6.9.5.19.2.5 UHS–I SDR50 Mode
            6. 6.9.5.19.2.6 UHS–I DDR50 Mode
            7. 6.9.5.19.2.7 UHS–I SDR104 Mode
        20. 6.9.5.20 CPTS
          1. 6.9.5.20.1 CPTS Timing Requirements
          2. 6.9.5.20.2 CPTS Switching Characteristics
        21. 6.9.5.21 OSPI
          1. 6.9.5.21.1 OSPI PHY Mode
            1. 6.9.5.21.1.1 OSPI With Data Training
              1. 6.9.5.21.1.1.1 OSPI Switching Characteristics – Data Training
            2. 6.9.5.21.1.2 OSPI Without Data Training
              1. 6.9.5.21.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 6.9.5.21.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 6.9.5.21.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 6.9.5.21.1.2.4 OSPI Switching Characteristics – DDR Mode
          2. 6.9.5.21.2 OSPI Tap Mode
            1. 6.9.5.21.2.1 OSPI Tap SDR Timing
            2. 6.9.5.21.2.2 OSPI Tap DDR Timing
        22. 6.9.5.22 PCIE
        23. 6.9.5.23 Timers
          1. 6.9.5.23.1 Timing Requirements for Timers
          2. 6.9.5.23.2 Switching Characteristics for Timers
        24. 6.9.5.24 UART
          1. 6.9.5.24.1 Timing Requirements for UART
          2. 6.9.5.24.2 UART Switching Characteristics
        25. 6.9.5.25 USB
      6. 6.9.6 Emulation and Debug
        1. 6.9.6.1 Trace
        2. 6.9.6.2 JTAG
          1. 6.9.6.2.1 JTAG Electrical Data and Timing
            1. 6.9.6.2.1.1 JTAG Timing Requirements
            2. 6.9.6.2.1.2 JTAG Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A72
      2. 7.2.2 Arm Cortex-R5F
      3. 7.2.3 DSP C71x
      4. 7.2.4 DSP C66x
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 GPU
      2. 7.3.2 VPAC
      3. 7.3.3 DMPAC
      4. 7.3.4 D5520MP2
      5. 7.3.5 VXE384MP2
    4. 7.4 Other Subsystems
      1. 7.4.1 MSMC
      2. 7.4.2 NAVSS
        1. 7.4.2.1 NAVSS0
        2. 7.4.2.2 MCU_NAVSS
      3. 7.4.3 PDMA Controller
      4. 7.4.4 Power Supply
      5. 7.4.5 Peripherals
        1. 7.4.5.1  ADC
        2. 7.4.5.2  ATL
        3. 7.4.5.3  CSI
          1. 7.4.5.3.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
          2. 7.4.5.3.2 Camera Streaming Interface Transmitter (CSI_TX_IF)
        4. 7.4.5.4  CPSW2G
        5. 7.4.5.5  CPSW9G
        6. 7.4.5.6  DCC
        7. 7.4.5.7  DDRSS
        8. 7.4.5.8  DSS
          1. 7.4.5.8.1 DSI
          2. 7.4.5.8.2 eDP
        9. 7.4.5.9  VPFE
        10. 7.4.5.10 eCAP
        11. 7.4.5.11 EPWM
        12. 7.4.5.12 ELM
        13. 7.4.5.13 ESM
        14. 7.4.5.14 eQEP
        15. 7.4.5.15 GPIO
        16. 7.4.5.16 GPMC
        17. 7.4.5.17 Hyperbus
        18. 7.4.5.18 I2C
        19. 7.4.5.19 I3C
        20. 7.4.5.20 MCAN
        21. 7.4.5.21 MCASP
        22. 7.4.5.22 MCRC Controller
        23. 7.4.5.23 MCSPI
        24. 7.4.5.24 MMC/SD
        25. 7.4.5.25 OSPI
        26. 7.4.5.26 PCIE
        27. 7.4.5.27 SerDes
        28. 7.4.5.28 WWDT
        29. 7.4.5.29 Timers
        30. 7.4.5.30 UART
        31. 7.4.5.31 USB
        32. 7.4.5.32 UFS
  9. 8 Applications and Implementation
    1. 8.1 Power Supply Mapping
    2. 8.2 Device Connection and Layout Fundamentals
      1. 8.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 8.2.1.1 Power Distribution Network Implementation Guidance
      2. 8.2.2 External Oscillator
      3. 8.2.3 JTAG and EMU
      4. 8.2.4 Reset
      5. 8.2.5 Unused Pins
      6. 8.2.6 Hardware Design Guide for JacintoTM 7 Devices
    3. 8.3 Peripheral- and Interface-Specific Design Information
      1. 8.3.1 LPDDR4 Board Design and Layout Guidelines
      2. 8.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 8.3.2.1 No Loopback and Internal Pad Loopback
        2. 8.3.2.2 External Board Loopback
        3. 8.3.2.3 DQS (only available in Octal Flash devices)
      3. 8.3.3 SERDES REFCLK Design Guidelines
      4. 8.3.4 USB VBUS Design Guidelines
      5. 8.3.5 System Power Supply Monitor Design Guidelines
      6. 8.3.6 High Speed Differential Signal Routing Guidance
      7. 8.3.7 Thermal Solution Guidance
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALF|827
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3.11.1 MAIN Domain

Table 5-62 CPSW9G0 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
CLKOUTRMII Clock Output (50 MHz). This pin is used for clock source to the external PHY and must be routed back to the RMII_REF_CLK pin for proper device operation.OZAA25, AJ28, Y29
MDIO0_MDCMDIO ClockOV24
MDIO0_MDIOMDIO DataIOV26
RGMII1_RXCRGMII Receive ClockIAD22
RGMII1_RX_CTLRGMII Receive ControlIAH23
RGMII1_TXCRGMII Transmit ClockOAE24
RGMII1_TX_CTLRGMII Transmit ControlOAC24
RGMII2_RXCRGMII Receive ClockIAE23
RGMII2_RX_CTLRGMII Receive ControlIAH24
RGMII2_TXCRGMII Transmit ClockOAJ26
RGMII2_TX_CTLRGMII Transmit ControlOAJ27
RGMII3_RXCRGMII Receive ClockIAE26
RGMII3_RX_CTLRGMII Receive ControlIAD25
RGMII3_TXCRGMII Transmit ClockOAH28
RGMII3_TX_CTLRGMII Transmit ControlOAG27
RGMII4_RXCRGMII Receive ClockIAC26
RGMII4_RX_CTLRGMII Receive ControlIAD29
RGMII4_TXCRGMII Transmit ClockOAG29
RGMII4_TX_CTLRGMII Transmit ControlOAF29
RGMII5_RXCRGMII Receive ClockIU25
RGMII5_RX_CTLRGMII Receive ControlIU26
RGMII5_TXCRGMII Transmit ClockOU29
RGMII5_TX_CTLRGMII Transmit ControlOU23
RGMII6_RXCRGMII Receive ClockIW26
RGMII6_RX_CTLRGMII Receive ControlIV23
RGMII6_TXCRGMII Transmit ClockOW29
RGMII6_TX_CTLRGMII Transmit ControlOY28
RGMII7_RXCRGMII Receive ClockIAD22
RGMII7_RX_CTLRGMII Receive ControlIAH23
RGMII7_TXCRGMII Transmit ClockOAE24
RGMII7_TX_CTLRGMII Transmit ControlOAC24
RGMII8_RXCRGMII Receive ClockIAE23
RGMII8_RX_CTLRGMII Receive ControlIAH24
RGMII8_TXCRGMII Transmit ClockOAJ26
RGMII8_TX_CTLRGMII Transmit ControlOAJ27
RGMII1_RD0RGMII Receive Data 0IAC23
RGMII1_RD1RGMII Receive Data 1IAG22
RGMII1_RD2RGMII Receive Data 2IAF22
RGMII1_RD3RGMII Receive Data 3IAJ23
RGMII1_TD0RGMII Transmit Data 0OAF24
RGMII1_TD1RGMII Transmit Data 1OAJ24
RGMII1_TD2RGMII Transmit Data 2OAG24
RGMII1_TD3RGMII Transmit Data 3OAD24
RGMII2_RD0RGMII Receive Data 0IAE22
RGMII2_RD1RGMII Receive Data 1IAG23
RGMII2_RD2RGMII Receive Data 2IAF23
RGMII2_RD3RGMII Receive Data 3IAD23
RGMII2_TD0RGMII Transmit Data 0OAJ25
RGMII2_TD1RGMII Transmit Data 1OAH25
RGMII2_TD2RGMII Transmit Data 2OAG25
RGMII2_TD3RGMII Transmit Data 3OAH26
RGMII3_RD0RGMII Receive Data 0IAF28
RGMII3_RD1RGMII Receive Data 1IAE28
RGMII3_RD2RGMII Receive Data 2IAE27
RGMII3_RD3RGMII Receive Data 3IAD26
RGMII3_TD0RGMII Transmit Data 0OAJ28
RGMII3_TD1RGMII Transmit Data 1OAH27
RGMII3_TD2RGMII Transmit Data 2OAH29
RGMII3_TD3RGMII Transmit Data 3OAG28
RGMII4_RD0RGMII Receive Data 0IAE29
RGMII4_RD1RGMII Receive Data 1IAD28
RGMII4_RD2RGMII Receive Data 2IAD27
RGMII4_RD3RGMII Receive Data 3IAC25
RGMII4_TD0RGMII Transmit Data 0OAG26
RGMII4_TD1RGMII Transmit Data 1OAF27
RGMII4_TD2RGMII Transmit Data 2OAF26
RGMII4_TD3RGMII Transmit Data 3OAE25
RGMII5_RD0RGMII Receive Data 0IT23
RGMII5_RD1RGMII Receive Data 1IR23
RGMII5_RD2RGMII Receive Data 2IU24
RGMII5_RD3RGMII Receive Data 3IU27
RGMII5_TD0RGMII Transmit Data 0OU28
RGMII5_TD1RGMII Transmit Data 1OV27
RGMII5_TD2RGMII Transmit Data 2OV29
RGMII5_TD3RGMII Transmit Data 3OV28
RGMII6_RD0RGMII Receive Data 0IW25
RGMII6_RD1RGMII Receive Data 1IW24
RGMII6_RD2RGMII Receive Data 2IY27
RGMII6_RD3RGMII Receive Data 3IY29
RGMII6_TD0RGMII Transmit Data 0OW27
RGMII6_TD1RGMII Transmit Data 1OV25
RGMII6_TD2RGMII Transmit Data 2OW28
RGMII6_TD3RGMII Transmit Data 3OW23
RGMII7_RD0RGMII Receive Data 0IAC23
RGMII7_RD1RGMII Receive Data 1IAG22
RGMII7_RD2RGMII Receive Data 2IAF22
RGMII7_RD3RGMII Receive Data 3IAJ23
RGMII7_TD0RGMII Transmit Data 0OAF24
RGMII7_TD1RGMII Transmit Data 1OAJ24
RGMII7_TD2RGMII Transmit Data 2OAG24
RGMII7_TD3RGMII Transmit Data 3OAD24
RGMII8_RD0RGMII Receive Data 0IAE22
RGMII8_RD1RGMII Receive Data 1IAG23
RGMII8_RD2RGMII Receive Data 2IAF23
RGMII8_RD3RGMII Receive Data 3IAD23
RGMII8_TD0RGMII Transmit Data 0OAJ25
RGMII8_TD1RGMII Transmit Data 1OAH25
RGMII8_TD2RGMII Transmit Data 2OAG25
RGMII8_TD3RGMII Transmit Data 3OAH26
RMII1_CRS_DVRMII Carrier Sense / Data ValidIAF22
RMII1_RX_ERRMII Receive Data ErrorIAJ23
RMII1_TX_ENRMII Transmit EnableOAD20
RMII2_CRS_DVRMII Carrier Sense / Data ValidIAF23
RMII2_RX_ERRMII Receive Data ErrorIAD23
RMII2_TX_ENRMII Transmit EnableOAJ25
RMII3_CRS_DVRMII Carrier Sense / Data ValidIAE27
RMII3_RX_ERRMII Receive Data ErrorIAD26
RMII3_TX_ENRMII Transmit EnableOAE26
RMII4_CRS_DVRMII Carrier Sense / Data ValidIAD27
RMII4_RX_ERRMII Receive Data ErrorIAC25
RMII4_TX_ENRMII Transmit EnableOAG26
RMII5_CRS_DVRMII Carrier Sense / Data ValidIAD21
RMII5_RX_ERRMII Receive Data ErrorIAE21
RMII5_TX_ENRMII Transmit EnableOAG21
RMII6_CRS_DVRMII Carrier Sense / Data ValidIAB23
RMII6_RX_ERRMII Receive Data ErrorIAC21
RMII6_TX_ENRMII Transmit EnableOAC22
RMII7_CRS_DVRMII Carrier Sense / Data ValidIU23
RMII7_RX_ERRMII Receive Data ErrorIU26
RMII7_TX_ENRMII Transmit EnableOU29
RMII8_CRS_DVRMII Carrier Sense / Data ValidIY28
RMII8_RX_ERRMII Receive Data ErrorIV23
RMII8_TX_ENRMII Transmit EnableOW29
RMII1_RXD0RMII Receive Data 0IAC23
RMII1_RXD1RMII Receive Data 1IAG22
RMII1_TXD0RMII Transmit Data 0OAH23
RMII1_TXD1RMII Transmit Data 1OAD22
RMII2_RXD0RMII Receive Data 0IAE22
RMII2_RXD1RMII Receive Data 1IAG23
RMII2_TXD0RMII Transmit Data 0OAH24
RMII2_TXD1RMII Transmit Data 1OAE23
RMII3_RXD0RMII Receive Data 0IAE28
RMII3_RXD1RMII Receive Data 1IAF28
RMII3_TXD0RMII Transmit Data 0OAC29
RMII3_TXD1RMII Transmit Data 1OAD25
RMII4_RXD0RMII Receive Data 0IAE29
RMII4_RXD1RMII Receive Data 1IAD28
RMII4_TXD0RMII Transmit Data 0OAC26
RMII4_TXD1RMII Transmit Data 1OAD29
RMII5_RXD0RMII Receive Data 0IAJ20
RMII5_RXD1RMII Receive Data 1IAG20
RMII5_TXD0RMII Transmit Data 0OAH21
RMII5_TXD1RMII Transmit Data 1OAJ21
RMII6_RXD0RMII Receive Data 0IY23
RMII6_RXD1RMII Receive Data 1IAF21
RMII6_TXD0RMII Transmit Data 0OAJ22
RMII6_TXD1RMII Transmit Data 1OAH22
RMII7_RXD0RMII Receive Data 0IT23
RMII7_RXD1RMII Receive Data 1IR23
RMII7_TXD0RMII Transmit Data 0OU28
RMII7_TXD1RMII Transmit Data 1OV27
RMII8_RXD0RMII Receive Data 0IW25
RMII8_RXD1RMII Receive Data 1IW24
RMII8_TXD0RMII Transmit Data 0OW27
RMII8_TXD1RMII Transmit Data 1OV25
RMII_REF_CLKRMII Reference ClockIAD18