8.3.1 LDO

The LDO (low-dropout) is an internal supply voltage regulator for the TDC7200. No external circuitry needs to be connected to the output of this regulator other than the mandatory external decoupling capacitor.

Recommendations for the decoupling capacitor parameters:

• Type: ceramic
• Capacitance: 0.4 µF–2.7 µF (1 µF typical). If using a capacitor value outside the recommended range, the part may malfunction and can be damaged.
• ESR: 100 mΩ (max)

8.3.2 CLOCK

TDC7200 needs an external reference clock connected to the CLOCK pin. The external CLOCK is used to calibrate the internal time base accurately and therefore, the measurement accuracy is heavily dependent on the external CLOCK accuracy. This reference clock is also used by all digital circuits inside the device; thus, CLOCK has to be available and stable at all times when the device is enabled (ENABLE = HIGH).

Figure 15 shows the typical effect of the external CLOCK frequency on the measurement uncertainty. With a reference clock of 1MHz, the standard deviation of a set of measurement results is approximately 243ps. As the reference clock frequency is increased, the standard deviation (or measurement uncertainty) reduces. Therefore, using a reference clock of 16MHz is recommended for optimal performance.

Figure 15. Standard Deviation vs. CLOCK

8.3.3 Counters

8.4.1 Calibration

The time measurements performed by the TDC7200 are based on an internal time base which is represented as the LSB value of the TIME1 to TIME6 results registers. The typical LSB value can be seen in Electrical Characteristics. However, the actual value of the LSB can vary depending on environmental variables (temperature, systematic noise, etc.). This variation can introduce significant error into the measurement result. There is also an offset error in the measurement due to certain internal delays in the device.

In order to compensate for these errors and to calculate the actual LSB value, calibration needs to be performed. The TDC7200 calibration consists of two measurement cycles of the external CLOCK. The first is a measurement of a single clock cycle period of the external clock; the second measurement is for the number of external CLOCK periods set by the CALIBRATION2_PERDIOS in the CONFIG2 register. The results from the calibration measurements are stored in the CALIBRATION1 and CALIBRATION2 registers.

The two-point calibration is used to determine the actual LSB in real time in order to convert the TIME1 to TIME6 results from number of delays to a real time-of-flight (TOF) number. As discussed in the next sections, the calibrations will be used for calculating time-of-flight (TOF) in measurement modes 1 and 2.

8.4.2 Measurement Modes

8.4.2.1 Measurement Mode 1

In measurement mode 1 as shown in Figure 16, the TDC7200 performs the entire counting from START to the last STOP using its internal ring oscillator plus coarse counter. This method is recommended for measuring shorter time durations of < 500 ns. Using measurement mode 1 for measuring time > 500ns decreases accuracy of the measurement (as shown in Figure 17), and is not recommended.

Figure 16. Measurement Mode 1

Figure 17. Measurement Mode 1 Standard Deviation vs. Measured Time-of-Flight

8.4.2.1.1 Calculating Time-of-Flight (Measurement Mode 1)

For measurement mode 1, the time-of-flight (TOF) between the START to the n^th STOP can be calculated using Equation 1:

Equation 1.

where

• TOF_n [sec] = time-of-flight measurement from the START to the n^th STOP
• TIME_n = n^th TIME measurement given by the TIME1 to TIME6 registers
• normLSB [sec] = normalized LSB value from calibration
• CLOCKperiod [sec] = external CLOCK period
• CALIBRATION1 [count] = TDC count for first calibration cycle
• CALIBRATION2 [count] = TDC count for second calibration cycle
• CALIBRATION2_PERIODS = setting for the second calibration cycle; located in register CONFIG2

For example, assume the time-of-flight between the START to the 1^st STOP is desired, and the following readouts were obtained:

• CALIBRATION2 = 21121 (decimal)
• CALIBRATION1 = 2110 (decimal)
• CALIBRATION2_PERIODS = 10
• CLOCK = 8MHz
• TIME1 = 4175 (decimal)

Therefore, the calculation for time-of-flight is:

• calCount = (21121 – 2110) / (10 – 1) = 2112.33
• normLSB = (1/8MHz) / (2112.33) = 5.917 x 10^-11
• TOF1 = (4175)(5.917 x 10^-11) = 247.061 ns

8.4.2.2 Measurement Mode 2

In measurement mode 2, the internal ring oscillator of the TDC7200 is used only to count fractional parts of the total measured time. As shown in Figure 18, the internal ring oscillator starts counting from when it receives the START signal until the first rising edge of the CLOCK. Then, the internal ring oscillator switches off, and the Clock counter starts counting the clock cycles of the external CLOCK input until a STOP pulse is received. The internal ring oscillator again starts counting from the STOP signal until the next rising edge of the CLOCK.

Figure 18. Measurement Mode 2

8.4.2.2.1 Calculating Time-of-Flight (TOF) (Measurement Mode 2)

The time-of-flight (TOF) between the START to the n^th STOP can be calculated using Equation 2:

Equation 2.

where

• TOF_n [sec] = time-of-flight measurement from the START to the n^th STOP
• TIME1 = time 1 measurement given by the TDC7200 register address 0x10
• TIME_(n+1) = (n+1) time measurement, where n = 1 to 5 (TIME2 to TIME6 registers)
• normLSB [sec] = normalized LSB value from calibration
• CLOCK_COUNT_n = nth clock count, where n = 1 to 5 (CLOCK_COUNT1 to CLOCK_COUNT5)
• CLOCKperiod [sec] = external CLOCK period
• CALIBRATION1 [count] = TDC count for first calibration cycle
• CALIBRATION2 [count] = TDC count for second calibration cycle
• CALIBRATION2_PERIODS = setting for the second calibration; located in register CONFIG2

For example, assume the time-of-flight between the START to the 1^st STOP is desired, and the following readouts were obtained:

• CALIBRATION2 = 23133 (decimal)
• CALIBRATION1 = 2315 (decimal)
• CALIBRATION2_PERIODS = 10
• CLOCK = 8MHz
• TIME1 = 2147 (decimal)
• TIME2 = 201 (decimal)
• CLOCK_COUNT1 = 318 (decimal)

Therefore, the calculation for time-of-flight is:

Equation 3.

8.4.3 Timeout

For one STOP, the TDC performs the measurement by counting from the START signal to the STOP signal. If no STOP signal is received, either the Clock Counter or Coarse Counter will overflow and will generate an interrupt (see Coarse and Clock Counters Overflow). If no START signal is received, the timer waits indefinitely for a START signal to arrive.

For multiple STOPs, the TDC performs the measurement by counting from the START signal to the last STOP signal. All earlier STOP signals are captured and stored into the corresponding Measurement Results registers (TIME1 to TIME6, CLOCK_COUNT1 to CLOCK_COUNT5, CALIBRATION1, CALIBRATION2). The minimum time required between two consecutive STOP signals is defined in the Recommended Operating Conditions table. The device can be programmed to measure up to 5 STOP signals by setting the NUM_STOP bits in the CONFIG2 register.

8.4.4 Multi-Cycle Averaging

In the Multi-Cycle Averaging Mode, the TDC7200 will perform a series of measurements on its own and will only send an interrupt to the MCU (for example, MSP430, C2000, etc) for wake up after the series has been completed. While waiting, the MCU can remain in sleep mode during the whole cycle (as shown in Figure 19).

Multi-Cycle Averaging Mode Setup and Conditions:

• The number of averaging cycles should be selected (1 to 128). This is done by programming the AVG_CYCLES bit in the CONFIG2 register.
• The results of all measurements are reported in the Measurement Results registers (TIME1 to TIME6, CLOCK_COUNT1 to CLOCK_COUNT5, CALIBRATION1, CALIBRATION2 registers). The CLOCK_COUNTn registers should be right shifted by the log2(AVG_CYCLES) before calculating the time-of-flight (TOF). For example, if using the multi-cycle averaging mode, Equation 2 should be rewritten as: TOFn = normLSB [TIME1 - TIME(n+1)] + [CLOCK_COUNTn >> log 2 (AVG_CYCLES)] x [CLOCKperiod]
• Following each average cycle, the TDC generates either a trigger event on the TRIGG pin after the calibration measurement to commence a new measurement or an interrupt on the INTB pin, indicating that the averaging sequence has completed.

This mode allows multiple measurements without MCU interaction, thus optimizing power consumption for the overall system.

Figure 19. Multi-Cycle Averaging Mode Example with 2 Averaging Cycles and 5 STOP Signals

8.4.5 START and STOP Edge Polarity

In order to achieve the highest measurement accuracy, having the same edge polarity for the START and STOP input signals is highly recommended. Otherwise, slightly different propagation delays due to symmetry shift between the rising and falling edge configuration will impact the measurement accuracy.

For highest measurement accuracy in measurement mode 2, it’s strongly recommended to choose for the START and STOP signal the “rising edge”. This is done by setting the START_EDGE and STOP_EDGE bits in the CONFIG1 register to 0.

8.4.6 Measurement Sequence

The TDC7200 is a stopwatch IC that measures time between a START and multiple STOP events. The measurement sequence of the TDC7200 is as follows:

1. After powering up the device, the EN pin needs to be low. There is one low to high transition required while VDD is supplied for correct initialization of the device.
2. MCU software requests a new measurement to be initiated via the SPI™ interface.
3. After the start new measurement bit START_MEAS has been set in the CONFIG1 register, the TDC7200 generates a trigger signal on the TRIGG pin, which is typically used by the corresponding ultrasonic analog-front-end (such as the TDC1000) as start trigger for a measurement (for example, transmit signal for the ultrasonic burst)
4. Immediately after sending the trigger, the TDC7200 enables the START pin and waits to receive the START pulse edge
5. After receiving a START, the TDC resets the TRIGG pin
6. The Clock counter is started after the next rising edge of the external clock signal (Measurement Mode 2). The Clock Counter STOP Mask registers (CLOCK_CNTR_STOP_MASK_H and CLOCK_CNTR_STOP_MASK_L) determine the length of the STOP mask window.
7. After reaching the Clock Counter STOP Mask value, the STOP pin waits to receive a single or multiple STOP trigger signal from the analog-front-end (for example, detected echo signal of the ultrasonic burst signal)
8. After the last STOP trigger has been received, the TDC will signal to the MCU via interrupt (INTB pin) that there are new measurement results waiting in the registers. START, STOP and TRIGG pin are disabled (in Multi-Cycle Averaging Mode, the TDC will start the next cycle automatically by generating a new TRIGG signal). Note: INTB must be utilized to determine TDC measurement completion; polling the INT_STATUS register to determine measurement completion is NOT recommended as it will interfere with the TDC measurement.
9. After the results are retrieved, the MCU can then start a new measurement with the same register settings. This is done by just setting the START measurement bit via SPI. It is not required to drive the ENABLE pin low between measurements.
10. The ENABLE pin can be taken low, if the time duration between measurements is long, and it is desired to put the TDC7200 in its lowest power state. However, upon taking ENABLE high again, the device will come up with its default register settings and will need to be configured via SPI.

8.4.7 Wait Times for TDC7200 Startup

The required wait time following the rising edge of the ENABLE pin of the TDC7200 is defined by three key times, as shown in Figure 20. All three times relate to the startup of the TDC7200’s internal LDO, which is power gated when the device is disabled for optimal power consumption. The first parameter, T1_{SPI_RDY}, is the time after which the SPI interface is accessible. The second (T2_{LDO_SET1}) parameter and third (T3_{LDO_SET2}) parameter are related to the performance of a measurement made while the internal LDO is settling. The LDO supplies the TDC7200’s time measurement device, and a change in voltage on its supply during a measurement translates directly to an inaccuracy. It is therefore recommended to wait until the LDO is settled before time measurement begins.

The first time period relating to the measurement accuracy is T2_{LDO_SET1}, the LDO settling time 1. This is the time after which the LDO has settled to within 0.3% of its final value. A 0.3% error translates to a worst case time error (due to the LDO settling) of 0.3% x t_CLOCK, which is 375ps in the case of an 8MHz reference clock, or 187.5ps if a 16MHz clock is used. Finally, the time T3_{LDO_SET2} is the time after which the LDO has settled to its final value. For best performance, it is recommended that a time measurement is not started before T3_{LDO_SET2} to allow the LDO to fully settle. Typical times for T1_{SPI_RDY} is 100 µs, for T2_{LDO_SET1} is 300 µs, and for T3_{LDO_SET2} is 1.5 ms.

Figure 20. VREG Startup Time

8.5.1 Serial Peripheral Interface (SPI)

The serial interface consists of data input (DIN), data output (DOUT), serial interface clock (SCLK), and chip select bar (CSB). The serial interface is used to configure the TDC7200 parameters available in various configuration registers.

The communication on the SPI bus supports write and read transactions. A write transaction consists of a single write command byte, followed by single data byte. A read transaction consists of a single read command byte followed by 8 or 24 SCLK cycles. The write and read command bytes consist of a 1-bit auto-increment bit, a 1-bit read or write instruction, and a 6-bit register address. Figure 21 shows the SPI protocol for a transaction involving one byte of data (read or write).

Figure 21. SPI Protocol

8.6.1 Register Initialization

After power up (VDD supplied, ENABLE Pin low to high transition) the internal registers are initialized with the default value. Disabling the part by pulling ENABLE pin to GND will set the device into total shutdown. As the internal LDO is turned off settings in the register will be lost. The device initializes the registers with default values with the next enable (ENABLE pin to VDD).

Table 1. Register Summary

8.6.2 CONFIG1: Configuration Register 1 R/W (address = 00h) [reset = 0h]

8.6.3 CONFIG2: Configuration Register 2 R/W (address = 01h) [reset = 40h]

8.6.4 INT_STATUS: Interrupt Status Register (address = 02h) [reset = 00h]

8.6.5 INT_MASK: Interrupt Mask Register R/W (address = 03h) [reset = 07h]

A disabled interrupt will no longer be visible on the device pin (INTB). The interrupt bit in the INT_STATUS register will still be active.

8.6.6 COARSE_CNTR_OVF_H: Coarse Counter Overflow High Value Register (address = 04h) [reset = FFh]

8.6.7 COARSE_CNTR_OVF_L: Coarse Counter Overflow Low Value Register (address = 05h) [reset = FFh ]

8.6.8 CLOCK_CNTR_OVF_H: Clock Counter Overflow High Register (address = 06h) [reset = FFh]

8.6.9 CLOCK_CNTR_OVF_L: Clock Counter Overflow Low Register (address = 07h) [reset = FFh]

8.6.10 CLOCK_CNTR_STOP_MASK_H: CLOCK Counter STOP Mask High Value Register (address = 08h) [reset = 00h]

8.6.11 CLOCK_CNTR_STOP_MASK_L: CLOCK Counter STOP Mask Low Value Register (address = 09h) [reset = 00h]

8.6.12 TIME1: Time 1 Register (address: 10h) [reset = 00_0000h]

8.6.13 CLOCK_COUNT1: Clock Count Register (address: 11h) [reset = 00_0000h]

8.6.14 TIME2: Time 2 Register (address: 12h) [reset = 00_0000h]

8.6.15 CLOCK_COUNT2: Clock Count Register (address: 13h) [reset = 00_0000h]

8.6.16 TIME3: Time 3 Register (address: 14h) [reset = 00_0000h]

8.6.17 CLOCK_COUNT3: Clock Count Registers (address: 15h) [reset = 00_0000h]

8.6.18 TIME4: Time 4 Register (address: 16h) [reset = 00_0000h]

8.6.19 CLOCK_COUNT4: Clock Count Register (address: 17h) [reset = 00_0000h]

8.6.20 TIME5: Time 5 Register (address: 18h) [reset = 00_0000h]

8.6.21 CLOCK_COUNT5: Clock Count Register (address: 19h) [reset = 00_0000h]

8.6.22 TIME6: Time 6 Register (address: 1Ah) [reset = 00_0000h]

8.6.23 CALIBRATION1: Calibration 1 Register (address: 1Bh ) [reset = 00_0000h]

8.6.24 CALIBRATION2: Calibration 2 Register (address: 1Ch ) [reset = 00_0000h]