SNAS686 May   2016 TDC7201

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 LDO
      2. 7.3.2 CLOCK
      3. 7.3.3 Counters
        1. 7.3.3.1 Coarse and Clock Counters Description
        2. 7.3.3.2 Coarse and Clock Counters Overflow
        3. 7.3.3.3 Clock Counter STOP Mask
        4. 7.3.3.4 ENABLE
    4. 7.4 Device Functional Modes
      1. 7.4.1 Calibration
      2. 7.4.2 Measurement Modes
        1. 7.4.2.1 Measurement Mode 1
          1. 7.4.2.1.1 Calculating Time-of-Flight (Measurement Mode 1)
        2. 7.4.2.2 Measurement Mode 2
          1. 7.4.2.2.1 Calculating Time-of-Flight (TOF) (Measurement Mode 2)
      3. 7.4.3 Timeout
      4. 7.4.4 Multi-Cycle Averaging
      5. 7.4.5 START and STOP Edge Polarity
      6. 7.4.6 Measurement Sequence
      7. 7.4.7 Wait Times for TDC7201 Startup
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI)
        1. 7.5.1.1 CSBx
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 DIN
        4. 7.5.1.4 DOUTx
        5. 7.5.1.5 Register Read/Write
        6. 7.5.1.6 Auto Increment Mode
    6. 7.6 Register Maps
      1. 7.6.1  Register Initialization
      2. 7.6.2  TDCx_CONFIG1: TDCx Configuration Register 1 R/W (address = 00h, CSBx asserted) [reset = 0h]
      3. 7.6.3  TDCx_CONFIG2: TDCx Configuration Register 2 R/W (address = 01h, CSBx asserted) [reset = 40h]
      4. 7.6.4  TDCx_INT_STATUS: Interrupt Status Register (address = 02h, CSBx asserted) [reset = 00h]
      5. 7.6.5  TDCx_INT_MASK: TDCx Interrupt Mask Register R/W (address = 03h, CSBx asserted) [reset = 07h]
      6. 7.6.6  TDCx_COARSE_CNTR_OVF_H: Coarse Counter Overflow High Value Register (address = 04h, CSBx asserted) [reset = FFh]
      7. 7.6.7  TDCx_COARSE_CNTR_OVF_L: TDCx Coarse Counter Overflow Low Value Register (address = 05h, CSBx asserted) [reset = FFh ]
      8. 7.6.8  TDCx_CLOCK_CNTR_OVF_H: Clock Counter Overflow High Register (address = 06h, CSBx asserted) [reset = FFh]
      9. 7.6.9  TDCx_CLOCK_CNTR_OVF_L: Clock Counter Overflow Low Register (address = 07h, CSBx asserted) [reset = FFh]
      10. 7.6.10 TDCx_CLOCK_CNTR_STOP_MASK_H: CLOCK Counter STOP Mask High Value Register (address = 08h, CSBx asserted) [reset = 00h]
      11. 7.6.11 TDCx_CLOCK_CNTR_STOP_MASK_L: CLOCK Counter STOP Mask Low Value Register (address = 09h, CSBx asserted) [reset = 00h]
      12. 7.6.12 TDCx_TIME1: Time 1 Register (address: 10h, CSBx asserted) [reset = 00_0000h]
      13. 7.6.13 TDCx_CLOCK_COUNT1: Clock Count Register (address: 11h, CSBx asserted) [reset = 00_0000h]
      14. 7.6.14 TDCx_TIME2: Time 2 Register (address: 12h, CSBx asserted) [reset = 00_0000h]
      15. 7.6.15 TDCx_CLOCK_COUNT2: Clock Count Register (address: 13h, CSBx asserted) [reset = 00_0000h]
      16. 7.6.16 TDCx_TIME3: Time 3 Register (address: 14h, CSBx asserted) [reset = 00_0000h]
      17. 7.6.17 TDCx_CLOCK_COUNT3: Clock Count Registers (address: 15h, CSBx asserted) [reset = 00_0000h]
      18. 7.6.18 TDCx_TIME4: Time 4 Register (address: 16h, CSBx asserted) [reset = 00_0000h]
      19. 7.6.19 TDCx_CLOCK_COUNT4: Clock Count Register (address: 17h, CSBx asserted) [reset = 00_0000h]
      20. 7.6.20 TDCx_TIME5: Time 5 Register (address: 18h, CSBx asserted) [reset = 00_0000h]
      21. 7.6.21 TDCx_CLOCK_COUNT5: Clock Count Register (address: 19h, CSBx asserted) [reset = 00_0000h]
      22. 7.6.22 TDCx_TIME6: Time 6 Register (address: 1Ah, CSBx asserted) [reset = 00_0000h]
      23. 7.6.23 TDCx_CALIBRATION1: Calibration 1 Register (address: 1Bh, CSBx asserted) [reset = 00_0000h]
      24. 7.6.24 TDCx_CALIBRATION2: Calibration 2 Register (address: 1Ch, CSBx asserted) [reset = 00_0000h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Measuring Time Periods Less Than 12 ns Using TDC7201
      3. 8.2.3 Application Curves
    3. 8.3 CLOCK Recommendations
      1. 8.3.1 CLOCK Accuracy
      2. 8.3.2 CLOCK Jitter
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

at TA = 25°C , VDD1 = VDD2 = 3.3 V, GND1 = GND2 = 0 V (unless otherwise noted).(1)(2)(3)(4)(5)
MIN MAX UNIT
VDD Supply voltage –0.3 3.9 V
VI Voltage on VREG1, VREG2 pins –0.3 1.65 V
Terminal input voltage on any other pin –0.3 VDD + 0.3
VDIFF_IN |Voltage differential| between any two input terminals 3.9 V
VIN_GND_VDD |Voltage differential| between any input terminal and GND or VDD 3.9 V
II Input current at any pin –5 5 mA
TA Ambient temperature –40 125 °C
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(3) All voltages are with respect to ground, unless otherwise specified.
(4) Pins VDD1 and VDD2 must be tied together at the board level and supplied from the same source.
(5) When the terminal input voltage (VI) at any pin exceeds power supplies (VI < GND or VI > VDD), the current at that pin must not exceed 5 mA (source or sink), and the voltage (VI) at the pin must not exceed 3.9 V.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

At TA = 25°C , VDD1 = VDD2 = 3.3 V, GND1 = GND2 = 0 V (unless otherwise noted).
MIN NOM MAX UNIT
VDD Supply voltage 2 3.6 V
VI Terminal voltage 0 VDD V
VIH Voltage input high 0.7 × VDD 3.6 V
VIL Voltage input low 0 0.3 × VDD V
FCALIB_CLK Frequency (reference or calibration clock) 1 (1) 8 16 MHz
tCLOCK Time period (reference or calibration clock) 62.5 125 1000 ns
DUTYCLOCK Input clock duty cycle 50%
TIMING REQUIREMENTS: Measurement Mode 1(1)(2)(3)
T1Min_STARTSTOP Minimum time between start and stop signal 12 ns
T1Max_STARTSTOP Maximum time between start and stop signal 2000 ns
T1Min_STOPSTOP Minimum time between 2 stop signals 67 ns
T1Max_LASTSTOP Maximum time between start and last stop signal 2000 ns
TIMING REQUIREMENTS: Measurement Mode 2(1)(2)(3)
T2Min_STARTSTOP Minimum time between start and stop signal 2 × tCLOCK s
T2Max_STARTSTOP Maximum time between start and stop signal (216-2) × tCLOCK s
T2Min_STOPSTOP Minimum time between 2 stop signals 2 × tCLOCK s
T2Max_LASTSTOP Maximum time between start and last stop signal (216-2) × tCLOCK s
TIMING REQUIREMENTS: ENABLE INPUT
TREN Rise time for enable signal (20% to 80%) 1 to 100 ns
TFEN Fall time for enable signal (20% to 80%) 1 to 100 ns
TIMING REQUIREMENTS: START1, STOP1, CLOCK, START2, STOP2
TRST, TFST Maximum rise, fall time for START, STOP signals
(20% to 80%)		 1 ns
TRXCLK, TFXCLK Maximum rise, fall time for external CLOCK
(20% to 80%)		 1 ns
TIMING REQUIREMENTS: TRIGG1, TRIGG2
TTRIG1START1 Time from TRIG1 to START1 5 ns
TTRIG2START2 Time from TRIG2 to START2 5 ns
TIMING REQUIREMENTS: Measurement Mode 1 Combined Operation(4)
T1STARTSTOP_Comb_Min Minimum time between START and STOP signal combined 0.25 ns
TEMPERATURE
TA Ambient temperature –40 85 °C
TJ Junction temperature –40 85 °C
(1) Specified by design.
(2) Applies to both pairs of START1, STOP1 and START2, STOP2 pins.
(3) Minimum time between 2 stop signals applies to 2 stop signals on the same TDC.
(4) TDC7201 device in combined measurement mode where START1 and START2 are connected together:
  1. A common REFERENCE_START signal is applied to START1 and START2 at least 12 ns before occurrence of actual START and STOP signals in Mode 1 (and at least 2 × tCLOCK before occurrence of actual Start and Stop signals in Mode 2).
  2. Start signal is connected to STOP1
  3. Stop signal is connected to STOP2
  4. Two time periods T1 (REFERENCE_START to Start) and T2 (REFERENCE_START to Stop) are measured and their difference (T2-T1) is the time between Start to Stop

6.4 Thermal Information

THERMAL METRIC(1) TDC7201 UNIT
ZAX (nFBGA)
25 PINS
RθJA Junction-to-ambient thermal resistance 155.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 109.5 °C/W
RθJB Junction-to-board thermal resistance 114.1 °C/W
ψJT Junction-to-top characterization parameter 20.8 °C/W
ψJB Junction-to-board characterization parameter 110.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

TA = 25°C , VDD1 = VDD2 = 3.3 V, GND1 = GND2 = 0 V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TDC CHARACTERISTICS
LSB Resolution Single shot measurement 55 ps
TACC-2 Accuracy (Mode 2)(1) CLOCK = 8 MHz, Jitter (RMS) < 1 ps, Stability < 5 ppm 28 ps
TSTD-2 Standard Deviation (Mode 2) Measured time = 100 µs 50 ps
Measured time = 1 µs 35 ps
OUTPUT CHARACTERISTICS: TRIGG1, TRIGG2, INTB1, INTB2, DOUT1, DOUT2
VOH Output voltage high Isource = –2 mA 2.31 2.95 V
VOL Output voltage low Isink = 2 mA 0.35 0.99 V
INPUT CHARACTERISTICS: START1, STOP1, START2, STOP2, CSB1, CSB2
Cin Input capacitance(2) 4 pF
INPUT CHARACTERISTICS: ENABLE, CLOCK, DIN, SCLK
Cin Input capacitance(2) 8 pF
POWER CONSUMPTION(3) (see Measurement Mode 1 and Measurement Mode 2)
Ish Shutdown current EN = LOW 0.6 µA
IQA Quiescent Current A EN = HIGH; TDC running 2.7 mA
IQB Quiescent Current B EN = HIGH; TDC OFF, Clock Counter running 140 µA
IQC Quiescent Current C EN = HIGH; measurement stopped, SPI communication only 175 µA
IQD Quiescent Current D EN = HIGH, TDC OFF, counter stopped, no communication 100 µA
(1) Accuracy is defined as the systematic error in the output signal; the error of the device excluding noise.
(2) Specified by design.
(3) Sum of TDC1 and TDC2 values

6.6 Timing Requirements

MIN NOM MAX UNIT
TIMING REQUIREMENTS: START1, STOP1, START2, STOP2, CLOCK
PWSTART Pulse width for Start Signal 10 ns
PWSTOP Pulse width for Stop Signal 10 ns
SERIAL INTERFACE TIMING CHARACTERISTICS (VDD = 3.3 V, fSCLK = 25 MHz) (See Figure 1)
fSCLK SCLK frequency 25 MHz
t1 SCLK period 40 ns
SERIAL INTERFACE TIMING CHARACTERISTICS (VDD = 3.3 V, fSCLK = 20 MHz) (See Figure 1)
t1 SCLK period 50 ns
t2 SCLK High Time 16 ns
t3 SCLK Low Time 16 ns
t4 DIN setup time 5 ns
t5 DIN hold time 5 ns
t6 CSB1 or CSB2 fall to SCLK rise 6 ns
t7 Last SCLK rising edge to CSB1 or CSB2 rising edge 6 ns
t8 Minimum pause time (CSB high) 40 ns
t9 Clk fall to DOUT1 or DOUT2 bus transition 12 ns

6.7 Switching Characteristics

TA = 25°C , VDD1 = VDD2 = 3.3 V, GND1 = GND2 = 0 V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
WAKE UP TIME
TWAKEUP_PERIOD Time to be ready for measurement LSB within 0.3% of settled value 300 µs
TDC7201 spi_register_write_snas686.gif Figure 1. SPI Register Access: 8 Bit Register Example

6.8 Typical Characteristics

At TA = 25°C , VDD1 = VDD2 = 3.3 V, GND1 = GND2 = 0 V, CLOCK = 8 MHz, CALIBRATION2_PERIODS = 10, AVG_CYCLES = 1 Measurement, NUM_STOP = Single STOP, Measurement Mode 2 (unless otherwise noted).
TDC7201 D001_SNAS647.gif
Figure 2. Time-of-Flight (TOF) vs VDD
(Measurement Mode 2)
TDC7201 D004_SNAS647.gif
Figure 4. TOF vs VDD
(Measurement Mode 1)
TDC7201 D022_SNAS647.gif
Figure 6. TOF vs. VDD (Mode 1 Combined Operation)
TDC7201 D006_SNAS647.gif
Figure 8. Resolution (LSB) vs VDD
TDC7201 D008_SNAS647.gif
Figure 10. Operating Current (IQA) vs VDD
TDC7201 D003_SNAS686.gif
Figure 12. Operating Current (IQB) vs VDD
TDC7201 D005_SNAS686.gif
Figure 14. Operating Current (IQC) vs VDD
TDC7201 D007_SNAS686.gif
Figure 16. Operating Current (IQD) vs VDD
TDC7201 D010_SNAS647.gif
Figure 18. Shutdown Current (ISH) vs VDD
TDC7201 D002_SNAS647.gif
Figure 3. TOF vs Temperature
(Measurement Mode 2)
TDC7201 D005_SNAS647.gif
Figure 5. TOF vs Temperature
(Measurement Mode 1)
TDC7201 D023_SNAS647.gif
Figure 7. TOF vs. Temperature (Mode 1 Combined Operation)
TDC7201 D007_SNAS647.gif
Figure 9. Resolution (LSB) vs Temperature
TDC7201 D011_SNAS647.gif
Figure 11. Operating Current (IQA) vs Temperature
TDC7201 D004_SNAS686.gif
Figure 13. Operating Current (IQB) vs Temperature
TDC7201 D006_SNAS686.gif
Figure 15. Operating Current (IQC) vs Temperature
TDC7201 D008_SNAS686.gif
Figure 17. Operating Current (IQD) vs Temperature
TDC7201 D013_SNAS647.gif
Figure 19. Shutdown Current (ISH) vs Temperature