SNLS697 Data sheet

SNLS697A April 2021 – February 2023 TDES954

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RGZ|48
- MPQF123F

Thermal pad, mechanical data (Package|Pins)

RGZ|48
- QFND014T

Orderable Information

7.4.27.2 Internally Generated FrameSync

In Internal FrameSync mode, an internally generated FrameSync signal is sent to one or more of the attached V³Link Serializers through a GPIO signal in the back channel.

FrameSync operation is controlled by the FS_CTL 0x18, FS_HIGH_TIME_x, and FS_LOW_TIME_x 0x19–0x1A registers. The resolution of the FrameSync generator clock (FS_CLK_PD) is derived from the back channel frame period (see BC_FREQ_SELECT[2:0] in Table 7-98). For example, each 50-Mbps back channel operation, the frame period is 600 ns (30 bits × 20 ns/bit), and for 2.5-Mbps back channel operation, the frame period is 12 µs (30 bits × 400 ns/bit).

Once enabled, the FrameSync signal is sent continuously based on the programmed conditions.

Enabling the internal FrameSync mode is done by setting the FS_GEN_ENABLE control in the FS_CTL register to a value of 1. The FS_MODE field controls the clock source used for the FrameSync generation. The FS_GEN_MODE field configures whether the duty cycle of the FrameSync is 50/50 or whether the high and low periods are controlled separately. The FrameSync high and low periods are controlled by the FS_HIGH_TIME and FS_LOW_TIME registers.

The accuracy of the internally generated FrameSync is directly dependent on the accuracy of the 25-MHz oscillator used as the reference clock and timing values should be scaled if reference other than 25 MHz is used.

Figure 7-18 Internal FrameSync

Figure 7-19 Internal FrameSync Signal

The following example shows generation of a FrameSync signal at 60 pulses per second. Mode settings:

Programmable High/Low periods: FS_GEN_MODE 0x18[1]=0
Use port 0 back channel frame period: FS_MODE 0x18[7:4]=0x0
Back channel rate of 50 Mbps: BC_FREQ_SELECT for port 0 0x58[2:0]=110b
Initial FS state of 0: FS_INIT_STATE 0x18[2]=0

Based on mode settings, the FrameSync is generated based upon FS_CLK_PD of 600 ns.

The total period of the FrameSync is (1 / 60 hz) / 600 ns or approximately 27,778 counts. The high time and low time are programmed to the desired value. For a 10% duty cycle, the high time should be 2,778 cycles and the low time should be 25,000 cycles.

For a 10% duty cycle, set the high time to 2,777 (0x0AD9) cycles, and the low time to 24,999 (0x61A7) cycles:

FS_HIGH_TIME_1: 0x19=0x0A
FS_HIGH_TIME_0: 0x1A=0xD9
FS_LOW_TIME_1: 0x1B=0x61
FS_LOW_TIME_0: 0x1C=0xA7