SNLS697 Data sheet

SNLS697A April 2021 – February 2023 TDES954

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RGZ|48
- MPQF123F

Thermal pad, mechanical data (Package|Pins)

RGZ|48
- QFND014T

Orderable Information

6.7 AC Electrical Characteristics CSI-2

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER		TEST CONDITIONS		PIN OR FREQUENCY	MIN	TYP	MAX	UNIT
HSTX DRIVER AC SPECIFICATIONS
HSTX_DBR	Data bit rate	REFCLK = 23 MHz		CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N	368	736	1472	Mbps
		REFCLK = 25 MHz			400	800	1600	Mbps
		REFCLK = 26 MHz			416	832	1664	Mbps
f_CLK	DDR clock frequency	REFCLK = 23 MHz		CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N	184	368	736	MHz
		REFCLK = 25 MHz			200	400	800	MHz
		REFCLK = 26 MHz			208	416	832	MHz
ΔV_CMTX(HF)	Common mode voltage variations HF	Common-level variations above 450MHz		CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N			15	mV_RMS
ΔV_CMTX(LF)	Common mode voltage variations LF	Common-level variations between 50 and 450MHz					25	mV_RMS
t_RHS t_FHS	20% to 80% rise and fall HS	HS bit rates ≤ 1 Gbps (UI ≥ 1 ns)		CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N			0.3	UI
		HS bit rates > 1 Gbps (UI					0.35	UI
		Applicable for all HS bit rates. However, to avoid excessive radiation, bit rates ≤ 1 Gbps (UI ≥ 1 ns), should not use values below 150 ps			100			ps
		Applicable for all HS bit rates when supporting > 1.5 Gbps					0.4	UI
		Applicable for all HS bit rates when supporting > 1.5 Gbps. However, to avoid excessive radiation, bit rates ≤ 1.5 Gbps should not use values below 100 ps and bit rates ≤ 1 Gbps should not use values below 150 ps.			50			ps
SDD_TX	TX differential return loss	f_LPMAX		CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N		–18		dB
		f_H	HSData rates < 1.5 Gbps			–9		dB
		f_H	HSData rates > 1.5 Gbps			-4.5		dB
		f_MAX	HSData rates < 1.5 Gbps			–-3		dB
		f_MAX	HSData rates > 1.5 Gbps			–-2.5		dB
SCC_TX	TX common mode return loss	f_LPMAX		CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N		–20		dB
		f_H				–15		dB
		f_MAX				–9		dB
LPTX DRIVER AC SPECIFICATIONS
t_RLP	Rise time LP	15% to 85% rise time		CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N			25	ns
t_FLP	Fall time LP	15% to 85% fall time					25	ns
t_REOT	Rise time post-EoT	30%-85% rise time					35	ns
t_LP-_PULSE-TX	Pulse width of the LP exclusive-OR clock	First LP exclusive-OR clock pulse after Stop state or last pulse before Stop state		CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N	40			ns
t_LP-_PULSE-TX	Pulse width of the LP exclusive-OR clock	All other pulses			20			ns
t_LP-PER-TX	Pulse width of the LP exclusive-OR clock				90			ns
DV/DtSR	Slew rate	CLoad = 0pF		CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N			500	mV/ns
		CLoad = 5pF					300	mV/ns
		CLoad = 20pF					250	mV/ns
		CLoad = 70pF					150	mV/ns
		CLoad = 0 to 70pF (Falling Edge Only) Data rate < 1.5 Gbps			30			mV/ns
		CLoad = 0 to 70pF (Rising Edge Only) Data rate < 1.5 Gbps			30			mV/ns
		CLoad = 0 to 70pF (Falling Edge Only) Data rate > 1.5 Gbps			25			mV/ns
		CLoad = 0 to 70pF (Rising Edge Only) Data rate > 1.5 Gbps			25			mV/ns
		CLoad = 0 to 70pF (Rising Edge Only) Applicable when the supported Data rate is < 1.5 Gbps			0 - 0.075 × (V_O,INST - 700)			mV/ns
		CLoad = 0 to 70pF (Rising Edge Only) Applicable when the supported Data rate is > 1.5 Gbps			25 - 0.0625 × (V_O,INST - 550)			mV/ns
CLOAD	Load capacitance			CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N	0		50	pF
DATA-CLOCK TIMING SPECIFICATIONS
UI_INST	UI instantaneous	In 1, 2, 3, or 4 Lane Configuration		CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N	0.6		2.7	ns
ΔUI	UI variation	UI ≥ 1ns			-10%		10%	UI
ΔUI	UI variation	0.667ns ≤ UI			-5%		5%	UI
t_SKEW(TX)	Data to Clock Skew (measured at transmitter) Skew between clock and data from ideal center	Data rate ≤ 1 Gbps		CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N	-0.15		0.15	UI_INST
t_SKEW(TX)		Data rate: 1 Gbps to 1.5 Gbps			-0.2		0.2	UI_INST
t_{SKEW(TX)STATIC}	Static Data to Clock Skew (TX)	Data rate > 1.5 Gbps		CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N	-0.2		0.2	UI_INST
t_{SKEW(TX)DYNAMIC}	Dynamic Data to Clock Skew (TX)				-0.15		0.15	UI_INST
ISI	Channel ISI						0.2	UI_INST
CSI-2 TIMING SPECIFICATIONS
t_CLK-MISS	Timeout for receiver to detect absence of clock transitions and disable the clock lane HS-RX			CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N	60			ns
t_CLK-POST	HS exit				60 + 52×UI			ns
t_CLK-PRE	Time HS clock shall be driver prior to any associated data lane beginning the transition from LP to HS mode				8			UI
t_CLK-PREPARE	Clock lane HS entry				38		95	ns
t_CLK-SETTLE	Time interval during which the HS receiver shall ignore any clock lane HS transitions				95		300	ns
t_CLK-TERM-EN	Time-out at clock lane display module to enable HS termination				Time for Dn to reach VTERM-EN		38	ns
t_CLK-TRAIL	Time that the transmitter drives the HS-0 state after the last payload clock bit of a HS transmission burst				60			ns
t_CLK-PREPARE + t_CLK-ZERO	TCLK-PREPARE + time that the transmitter drives the HS-0 state prior to starting the clock				300			ns
t_D-TERM-EN	Time for the data lane receiver to enable the HS line termination			CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N	Time for Dn to reach V_TERM-EN		35 + 4×UI	ns
t_EOT	Transmitted time interval from the start of tHS-TRAIL to the start of the LP-11 state following a HS burst						105 + 12×UI	ns
t_HS-EXIT	Time that the transmitter drives LP-11 following a HS burst				100			ns
t_HS-PREPARE	Data lane HS entry				40 + 4×UI		85 + 6×UI	ns
t_HS-_PREPARE + t_HS-ZERO	t_HS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence				145 + 10×UI			ns
t_HS-SETTLE	Time interval during which the HS receiver shall ignore any data lane HS transitions, starting from the beginning of tHS-SETTLE				85 + 6×UI		145 + 10×UI	ns
t_HS-SKIP	Time interval during which the HS-RX should ignore any transitions on the data lane, following a HS burst. The end point of the interval is defined as the beginning of the LP-11 state following the HS burst.				40		55 + 4×UI	ns
t_HS-TRAIL	Data lane HS exit				60 + 4×UI			ns
t_LPX	Transmitted length of LP state				50			ns
t_WAKEUP	Recovery Time from Ultra Low Power State (ULPS)				1			ms
t_INIT	Initialization period				100			µs