The TDES954 is a versatile dual deserializer hub capable of receiving serialized sensor data from one or two independent sources through a V3Link interface. When paired with a TSER953 serializer, the TDES954 receives data from imagers, supporting 2MP/60fps and 4MP/30fps cameras as well as satellite RADAR and other sensors such as ToF and LIDAR. Data is received and aggregated into a MIPI CSI-2 compliant output for interconnect to a downstream processor. For sensors with DVP Mode serializers, the TDES954 receives and aggregates data from one or two sensors including Full HD 1080p 2MP 60/fps imager sensors. When configuring the CSI-2 interface for 2-lane operation, a duplicate MIPI CSI-2 clock lane is available to provide a replicated output. Replication mode creates two copies of the aggregated video stream for data logging and parallel processing.
The TDES954 and partner TSER953 chipset is designed to receive data across either 50-Ω single-ended coaxial or 100-Ω differential STP cables. The deserializer hub is ideal for Power-over-Coax applications and the receive equalizer automatically adapts to compensate for cable loss characteristics with no additional programming required, including cable degradation over time.
Each V3Link interface includes a separate low latency bidirectional control channel (BCC) that continuously conveys I2C, GPIO, and other control information. GPIO signals purposed for sensor synchronization and diagnostic features also make use of the BCC.
PART NUMBER | PACKAGE (1) | BODY SIZE (NOM) |
---|---|---|
TDES954 | VQFN (48) | 7.00 mm × 7.00 mm |
Changes from Revision * (April 2021) to Revision A (February 2023)
PIN | I/O TYPE(1) |
DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
RECEIVE DATA CSI-2 OUTPUT | |||
CSI_D3P | 24 | O | RECEIVE DATA OUTPUT: This signal carries data from the V3Link Deserializer to the processor over CSI-2 interface. Receive data is CSI-2 configured with DPHY outputs as one differential clock lane (CSI_CLK0P/N) and up to four differential data lanes (CSI_D0P/N: CSI_D3P/N) or two clock lanes (CSI_CLK0P/N, CSI_CLK1P/N) and two differential data lanes for each clock. When in replicate mode data lanes CSI_D2P/N and CSI_D3P/N are associated with clock lane CSI_CLK1P/N to provide the replicated output. For unused outputs leave as No Connect. |
CSI_D3N | 23 | ||
CSI_D2P | 22 | ||
CSI_D2N | 21 | ||
CSI_CLK1P | 19 | ||
CSI_CLK1N | 18 | ||
CSI_D1P | 16 | ||
CSI_D1N | 15 | ||
CSI_D0P | 14 | ||
CSI_D0N | 13 | ||
CSI_CLK0P | 12 | ||
CSI_CLK0N | 11 | ||
CLOCK INTERFACE | |||
XOUT | 4 | O | Crystal oscillator output: Output Pin for providing crystal oscillator reference. Leave this pin NC when reference clock input is driving XIN/REFCLK. |
XIN/REFCLK | 5 | S, I | Reference clock input or crystal oscillator input. Pin is shared with XIN and REFCLK. Typically REFCLK connected to 23- to 26-MHz reference oscillator output (100 ppm) or XIN configured with external 23- to 26-MHz crystal to XOUT. See GUID-F0AAF502-058D-4C48-915B-6EF0781798F9.html. |
SYNCHRONIZATION AND GPIO | |||
GPIO0 | 28 | I/O, PD | General-Purpose Input/Output: Pins can be used to control and respond to various commands. They may be configured to be the input signals for the corresponding GPIOs on the serializer or they may be configured to be outputs to follow local register settings. At power up, the GPIO are disabled and by default include a 35-k (typical) pulldown resistor. See GUID-738FDFE7-F601-467D-9C5A-745339621EC6.html#GUID-738FDFE7-F601-467D-9C5A-745339621EC6 for programmability. Unused GPIO can be left open or no connect. |
GPIO1 | 27 | ||
GPIO2 | 26 | ||
GPIO4 | 10 | ||
GPIO5 | 9 | ||
GPIO6 | 8 | ||
GPIO3/INTB | 25 | I/O, OD | General-Purpose Input/Output: Pin GPIO3 can be configured to be input signals for GPOs on the Serializer. Pin 25 is shared with INTB. Pullup with 4.7 kΩ to V(VDDIO). The programmable input and output pin is an active-low open drain and controlled by the status registers. See GUID-738FDFE7-F601-467D-9C5A-745339621EC6.html#GUID-738FDFE7-F601-467D-9C5A-745339621EC6 for programmability. Unused GPIO can be left open or no connect. |
V3LINK INTERFACE | |||
RIN0+ | 41 | I/O | Receive Input Channel 0: Differential V3Link receiver and bidirectional control back channel output. The IO must be AC coupled. See Design Requirements for the correct AC-coupling capacitor values. If port is unused, leave NC and set RX_PORT_CTL register bit 0 = 0 to disable (see GUID-6CAF2430-C996-49EE-84D5-7656DF6902A2.html#GUID-6CAF2430-C996-49EE-84D5-7656DF6902A2). |
RIN0– | 42 | ||
RIN1+ | 32 | I/O | Receive Input Channel 1: Differential V3Link receiver and bidirectional control back channel output. The IO must be AC coupled. See Design Requirements for the correct AC-coupling capacitor values. If port is unused, leave NC and set RX_PORT_CTL register bit 1 = 0 to disable (see GUID-6CAF2430-C996-49EE-84D5-7656DF6902A2.html#GUID-6CAF2430-C996-49EE-84D5-7656DF6902A2). |
RIN1– | 33 | ||
I2C PINS | |||
I2C_SCL | 2 | I/O, OD | I2C Serial
Clock: Clock line for the bidirectional control
bus communication. External 2-kΩ to 4.7-kΩ pullup resistor to 1.8-V or 3.3-V supply rail recommended per I2C interface standards. I2C_SCL and I2C_SDA inputs are 3.3-V tolerant. See GUID-E4BFA389-69B3-44B4-9978-0ECF1CF2CBB4.html#GUID-E4BFA389-69B3-44B4-9978-0ECF1CF2CBB4 for more information. |
I2C_SDA | 1 | I/O, OD | I2C Serial
Data: Data line for bidirectional control bus
communication. External 2-kΩ to 4.7-kΩ pullup resistor to 1.8-V or 3.3-V supply rail recommended per I2C interface standards. I2C_SCL and I2C_SDA inputs are 3.3-V tolerant. See GUID-E4BFA389-69B3-44B4-9978-0ECF1CF2CBB4.html#GUID-E4BFA389-69B3-44B4-9978-0ECF1CF2CBB4 for more information. |
CONFIGURATION AND CONTROL PINS | |||
VDD_SEL | 46 | S, PD | VDD Select: Configuration pin to select internal LDO regulator supply. When VDD_SEL = LOW, internal 1.1-V supply mode is selected. Feed 1.8 V to VDD18 inputs = 1.8 V ±5%. An internal 1.1-V regulator will supply the VDD11. VDD11 inputs should be terminated with bypass capacitors. When VDD_SEL = HIGH, external 1.1-V supply mode is selected. After 1.8-V supply is applied to VDD18 inputs, then apply 1.1 V to VDD11 inputs = 1.1 V ±5%. Voltage at VDD11 supply pins must always be less than main voltage applied to VDD18 when using external 1.1-V supply. |
IDX | 35 | S, PD | Input. I2C
Serial Control Bus Primary Device ID Address
Select. Once enabled the voltage at this pin will be sampled to configure the default I2C device address. Typically connected with external pullup resistor to VDD18 and pulldown resistor to GND to create a voltage divider. See Table 7-15. |
MODE | 37 | S, PD | Mode select
configuration input to set operating mode based on
input voltage level. Typically connected to voltage divider through external pullup to VDD18 and pulldown to GND. See Table 7-1. |
PDB | 30 | I, PD | Power-down
inverted Input Pin. Typically connected to processor GPIO with pull down. When PDB
input is brought HIGH, the device is enabled and internal register and state
machines are reset to default values. Asserting PDB signal low will power down the
device and consume minimum power with CSI-2 Tx outputs in tri-state. The default
function of this pin is PDB = LOW; POWER DOWN with internal 50 kΩ pull down enabled.
PDB should remain low until after power supplies are applied and reach minimum
required levels. PDB INPUT IS 3.3-V TOLERANT. See section GUID-A91AC687-C9BE-404B-9AB5-A1A04061A79E.html#GUID-A91AC687-C9BE-404B-9AB5-A1A04061A79E. PDB = 1.8 V, device is enabled (normal operation) PDB = 0, device is powered down. |
DIAGNOSTIC PINS | |||
CMLOUTP | 38 | O | Monitor Loop-Through Driver differential output. Typically routed to test points and not connected. For monitoring, CMLOUT should be terminated with 100-Ω differential load. See GUID-27182324-B396-4996-8C03-B1000F599524.html#GUID-27182324-B396-4996-8C03-B1000F599524. |
CMLOUTN | 39 | ||
BISTEN | 6 | S, PD | BIST Enable: BISTEN = H, BIST Mode is enabled BISTEN = L, BIST Mode is disabled. If unused connect BISTEN directly to GND. See BIST section GUID-0A43E37C-81D9-4282-9131-8F519EC491ED.html#GUID-0A43E37C-81D9-4282-9131-8F519EC491ED for more information. |
PASS | 47 | O | PASS Output: PASS = H indicates pass conditions are met and PASS = L signals or more pass condition is not met. Typically route to processor input pin or test point for monitoring. May also be configured to indicate logical AND of pass status when both Rx ports are enabled. See GUID-71D29BA1-A93B-4769-8DE0-043AB2F337BA.html#GUID-71D29BA1-A93B-4769-8DE0-043AB2F337BA for more information. For BIST operation PASS = H, ERROR FREE Transmission in forward channel operation. PASS = L, one or more errors were detected in the received payload. See BIST section for more information. Leave No Connect if unused. |
LOCK | 48 | O | LOCK Status: Output Pin for monitoring lock status of V3Link channel, may be used as Link Status. LOCK = H, the V3Link receiver is Locked and Rx Ports are active. LOCK = L, receiver is unlocked. May also be configured to indicate logical AND of lock status when both Rx ports are enabled. See GUID-71D29BA1-A93B-4769-8DE0-043AB2F337BA.html#GUID-71D29BA1-A93B-4769-8DE0-043AB2F337BA for more information. Leave No Connect if unused. |
RES | 44 | PD | RES must be tied to GND for normal operation. |
POWER AND GROUND | |||
VDDIO | 7,29 | P | VDDIO voltage supply input: The single-ended outputs and control input are powered from VDDIO. VDDIO can be connected to either a 1.8-V or 3.3-V supply rail. When VDDIO is connected to 1.8-V supply, VDDIO must be within ±100 mV of VDD18 to ensure output timing requirements are met. Each VDDIO pin requires a minimum 1-µF and 0.01-µF capacitor to GND. Additional 0.1-μF decoupling is recommended for the pin group. |
VDD18_CSI | 17 | P | 1.8-V (±5%)
Power Supply. Requires 1-µF and 0.01-µF capacitors to GND. |
VDD18_P0 VDD18_P1 |
45 36 |
P | 1.8-V(±5%) Power Supplies. Requires 0.01-µF capacitors to GND at each VDD pin along with 10-µF bulk decoupling. Additional 0.1-μF decoupling is recommended for the pin group. |
VDD18_FPD0 VDD18_FPD1 |
40 31 |
P | 1.8-V(±5%)
Analog Power Supplies. Requires 10-µF, and 0.1-µF capacitors to GND at each VDD pin. Additional 0.01-μF decoupling is recommended for the pin group. |
VDD11_FPD0 | 43 | D, P | When VDD_SEL = LOW: Do not connect to 1.1-V power rail Requires 0.1 to 0.01-µF capacitor and a 4.7-µF capacitor to GND When VDD_SEL = HIGH: Connect to external 1.1-V power rail Requires a 0.01-μF capacitor to GND Requires a 10-μF capacitor to GND shared with VDD11_FPD1 See sections Power Supply Recommendations and Typical Application for more information |
VDD11_FPD1 | 34 | D, P | When VDD_SEL = LOW: Do not connect to 1.1-V power rail Requires a 0.1 to 0.01-µF capacitor and a 4.7-µF capacitor to GND When VDD_SEL = HIGH: Connect to external 1.1-V power rail Requires a 0.01-μF capacitor to GND Requires a 10-μF capacitor to GND shared with VDD11_FPD0 |
VDD11_CSI | 20 | D, P | When VDD_SEL = LOW: Do not connect to 1.1-V power rail Requires a 0.1 to 0.01-µF capacitor and a 4.7-µF capacitor to GND When VDD_SEL = HIGH: Connect to external 1.1-V power rail Requires a 0.01-μF capacitor and a 10-μF capacitor to GND |
VDD11_D | 3 | D, P | When VDD_SEL = LOW: Do not connect to 1.1-V power rail Requires a 0.1 to 0.01-µF capacitor and a 4.7-µF capacitor to GND When VDD_SEL = HIGH: Connect to external 1.1-V power rail Requires a 0.01-μF capacitor and a 1-μF capacitor to GND |
GND | DAP | G | DAP is the large metal contact at the bottom side, located at the center of the QFN package. Connect to the ground plane (GND). |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Supply voltage | VDD18 (VDD18_CSI, VDD18_P1 , VDD18_P0 , VDD18_FPD0, VDD18_FPD1) | –0.3 | 2.16 | V | |
VDD11 (VDD11_CSI, VDD11_D , VDD11_FPD0, VDD11_FPD1) | –0.3 | 1.32 and < V(VDD18) |
V | ||
VDDIO | –0.3 | 3.96 | V | ||
V3Link input voltage | RIN0+, RIN0–, RIN1+, RIN1– | Device powered up (VDD18, VDD11 and VDDIO within recommended operating conditions) | –0.3 | 2.75 | V |
Device powered down (VDD18, VDD11 and VDDIO below recommended operating conditions) Transient Voltage | –0.3 | 1.45 | V | ||
Device powered down (VDD18, VDD11 and VDDIO below recommended operating conditions) DC Voltage | –0.3 | 1.35 | V | ||
LVCMOS IO voltage | GPIO0, GPIO1, GPIO2, GPIOI4, GPIO5, GPIO6, XIN/REFCLK, VDD_SEL, XOUT, BISTEN, LOCK, PASS, CSI_D3P/N, CSI_D2P/N, CSI_D1P/N, CSI_D0P/N, CSI_CLK1P/N, CSI_CLK0P/N | –0.3 | V(VDDIO)+ 0.3 | V | |
PDB | –0.3 | 3.96 | V | ||
Configuration input voltage | MODE, IDX | –0.3 | V(VDD18)+ 0.3 | V | |
Open-drain voltage | GPIO3/INTB, I2C_SDA, I2C_SCL | –0.3 | 3.96 | V | |
Junction temperature | 150 | °C | |||
Storage temperature, Tstg | -65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM)(1) | All pins except 32, 33, 41 and 42 | ±4500 | V |
Pins 32, 33, 41 and 42 | ±8000 | ||||
Charged device model (CDM) | ±1250 | ||||
IEC 61000-4-2, powered-up only RD = 330 Ω , CS = 150 pF | Contact Discharge (RIN0+, RIN0-, RIN1+, RIN1-) | ±8000 | |||
Air Discharge (RIN0+, RIN0-, RIN1+, RIN1- | ±18000 | ||||
ISO 10605 RD= 330 Ω, CS= 150 pF and 330 pF RD= 2 kΩ, CS= 150 pF and 330 pF | Contact Discharge (RIN0+, RIN0-, RIN1+, RIN1-) | ±8000 | |||
Air Discharge (RIN0+, RIN0-, RIN1+, RIN1-) | ±18000 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Supply voltage | V(VDD18) | 1.71 | 1.8 | 1.89 | V |
V(VDD11) (VDD_SEL = HIGH ONLY) | 1.045 | 1.1 | 1.155 | V | |
Supply voltage offset | V(VDD11) - V(VDDIO), V(VDDIO) = 1.8V | -50 | 50 | mV | |
LVCMOS supply voltage | V(VDDIO) = 1.8 V OR V(VDDIO) = 3.3 V | 1.71 | 1.8 | 1.89 | V |
3 | 3.3 | 3.6 | V | ||
Open-drain voltage | GPIO3/INTB = V(INTB), I2C_SDA, I2C_SCL = V(I2C) | 1.71 | 3.6 | V | |
Operating free-air temperature, TA | –20 | 25 | 85 | °C | |
MIPI data rate (per CSI-2 lane) | 368 | 1664 | Mbps | ||
MIPI CSI-2 HS clock frequency | 184 | 832 | MHz | ||
Reference clock oscillator frequency | REFCLK or XIN/XOUT | 23 | 26 | MHz | |
Spread-spectrum reference clock modulation percentage | Center Spread | -0.5 | 0.5 | % | |
Down Spread | -1 | 0 | % | ||
Local I2C frequency, fI2C | 1 | MHz | |||
Supply noise(1) | V(VDD11) | 25 | mVP-P | ||
V(VDD18) | 50 | mVP-P | |||
V(VDDIO) = 1.8 V | 50 | mVP-P | |||
V(VDDIO) = 3.3 V | 100 | ||||
RIN0+, RIN1+ | 10 | mVP-P |
THERMAL METRIC(1) | TDES954 | UNIT | |
---|---|---|---|
RGC (VQFN) | |||
48 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 30.2 | °C/W |
RθJC(TOP) | Junction-to-case (top) thermal resistance | 15.7 | °C/W |
RθJC(BOT) | Junction-to-case (bottom) thermal resistance | 1.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 6.7 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 6.7 | °C/W |
PARAMETER | TEST CONDITIONS | PIN OR FREQUENCY | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
TOTAL POWER CONSUMPTION | ||||||||
PT | Total power consumption for MIPI CSI-2 output mode, normal operation | 2 x V3Link Input, V3Link
line-rate = 4.0 Gbps CSI-2 line-rate = 1.6 Gbps, CSI-2 = 4 DATA lanes + 1 CLK lane VDD_SEL = LOW, default registers |
V(VDD18)= 1.89 V, V(VDDIO) = 3.6 V | 473 | 564 | mW | ||
2 x V3Link Input, V3Link
line-rate = 4.0 Gbps CSI-2 line-rate = 1.6 Gbps, CS-I2 = 4 DATA lanes + 1 CLK lane VDD_SEL = HIGH, default registers |
V(VDD18)= 1.89 V, V(VDD11) = 1.155 V V(VDDIO) = 3.6 V | 450 | mW | |||||
DESERIALIZER SUPPLY CURRENT - V3Link Rx Port0 AND Rx Port1 PAIRED WITH 2x TSER953 |
||||||||
IDD-R2T4 | Deserializer supply current 2 Rx 4 Tx | 2 x V3Link Input,
V3Link line-rate = 4.0 Gbps per Rx port CSI-2 line-rate = 1.6 Gbps per lane, CSI-2 = 4 DATA lanes + 1 CLK lane VDD_SEL=LOW, default registers, includes CSI-2 load current |
VDD18 | 240 | 279 | mA | ||
VDDIO | 5 | 10 | ||||||
2 x V3Link Input,
V3Link line-rate = 4.0 Gbps per Rx port CSI-2 line-rate = 1.6 Gbps per lane, CSI-2 = 4 DATA lanes + 1 CLK lane VDD_SEL=HIGH, default registers, includes CSI-2 load current |
VDD18 | 110 | 140 | mA | ||||
VDD11 | 100 | 130 | ||||||
VDDIO | 5 | 10 | ||||||
IDD-R2T22 | Deserializer supply current 2 Rx 2x2 Tx | 2 x V3Link Input,
V3Link line-rate = 4.0 Gbps per Rx port CSI-2 line-rate = 1.6 Gbps, Replicate mode, CSI-2 = 2x 2 DATA lanes and 2x 1 CLK lanes VDD_SEL=LOW, includes CSI-2 load current |
VDD18 | 240 | 279 | mA | ||
VDDIO | 5 | 10 | ||||||
2 x V3Link Input,
V3Link line-rate = 4.0 Gbps per Rx port CSI-2 line-rate = 1.6 Gbps, Replicate mode, CSI-2 = 2x 2 DATA lanes and 2x 1 CLK lanes VDD_SEL=HIGH , includes CSI-2 load current |
VDD18 | 110 | 140 | mA | ||||
VDD11 | 100 | 130 | ||||||
VDDIO | 5 | 10 | ||||||
DESERIALIZER SUPPLY CURRENT - V3Link Rx Port0 OR Rx Port1 PAIRED WITH 1x TSER953 |
||||||||
IDD-R1T4 | Deserializer supply current 1 Rx 4 Tx | 1 x V3Link Input,
V3Link line-rate = 4.0 Gbps CSI-2 line-rate = 800 Mbps per lane, CSI-2 = 4 DATA lanes + 1 CLK lane VDD_SEL=LOW, default registers, includes CSI-2 load current |
VDD18 | 170 | 188 | mA | ||
VDDIO | 5 | 10 | ||||||
1 x V3Link Input,
V3Link line-rate = 4.0 Gbps CSI-2 line-rate = 800 Mbps per lane, CSI2 = 4 DATA lanes + 1 CLK lane VDD_SEL=HIGH, default registers, includes CSI-2 load current |
VDD18 | 65 | 80 | mA | ||||
VDD11 | 80 | 100 | ||||||
VDDIO | 5 | 10 | ||||||
DESERIALIZER SUPPLY CURRENT - V3Link Rx Port0 AND Rx Port1 PAIRED WITH 2x DVP Mode Serializers |
||||||||
IDD2-R2T4 | Deserializer supply current 2G 2 Rx 4 Tx | 2 x V3Link Input,
V3Link line-rate = 1.867 Gbps per Rx port CSI-2 line-rate = 800 Mbps, CSI-2 = 4 DATA lanes + 1 CLK lanes VDD_SEL=LOW, includes CSI-2 load current |
VDD18 | 220 | 265 | mA | ||
VDDIO | 5 | 10 | ||||||
2 x V3Link Input,
V3Link line-rate = 1.867 Gbps per Rx port CSI-2 line-rate = 800 Mbps, CSI-2 = 4 DATA lanes + 1 CLK lanes VDD_SEL=HIGH, includes CSI-2 load current |
VDD18 | 110 | 148 | mA | ||||
VDD11 | 85 | 100 | ||||||
VDDIO | 5 | 10 | ||||||
DESERIALIZER SUPPLY CURRENT - V3Link Rx Port0 OR Rx Port1 PAIRED WITH 1x DVP Mode Serializer |
||||||||
IDD2-R1T4 | Deserializer supply current 2G 1 Rx 4 Tx | 1 x V3Link Input,
V3Link line-rate = 1.867 Gbps CSI-2 line-rate = 800 Mbps, CSI-2 = 4 DATA lanes + 1 CLK lane VDD_SEL=LOW, includes CSI-2 load current |
VDD18 | 150 | 205 | mA | ||
VDDIO | 5 | 10 | ||||||
1 x V3Link Input,
V3Link line-rate = 1.867 Gbps CSI-2 line-rate = 800 Mbps, CSI-2 = 4 DATA lanes + 1 CLK lane VDD_SEL=HIGH, includes CSI-2 load current |
VDD18 | 65 | 86 | mA | ||||
VDD11 | 75 | 110 | ||||||
VDDIO | 5 | 10 | ||||||
DESERIALIZER SUPPLY CURRENT - Power Down |
||||||||
IDDZ | Deserializer shutdown current | PDB = HIGH to LOW, VDD_SEL = LOW | VDD18 | 82 | 115 | mA | ||
VDIO | 2.5 | 5 | ||||||
PDB = HIGH to LOW, VDD_SEL = HIGH | VDD18 | 10 | 15 | |||||
VDD11 | 30 | 110 | ||||||
VDDIO | 2.5 | 5 | ||||||
1.8-V LVCMOS I/O | ||||||||
VOH | High level output voltage | IOH = –2 mA, V(VDDIO) = 1.71 to 1.89 V; V(VDDIO) = VDD18 ±50 mV | GPIO[6:4], GPIO[2:0], LOCK, PASS | V(VDDIO) – 0.45 | V(VDDIO) | V | ||
VOL | Low level output voltage | IOL = 2 mA, V(VDDIO) = 1.71 to 1.89 V; V(VDDIO) = VDD18 ±50 mV | GPIO[6:0], LOCK, PASS | GND | 0.45 | V | ||
VIH | High level input voltage | V(VDDIO) = 1.71 to 1.89 V; V(VDDIO) = VDD18 ±50 mV | GPIO[6:0], BISTEN | 0.65 × V(VDDIO) |
V(VDDIO) | V | ||
V(VDDIO) = 1.71 to 1.89 V; V(VDDIO) = VDD18 ±50 mV | PDB, XIN/REFCLK, VDD_SEL |
1.17 | V(VDDIO) | V | ||||
VIL | Low level input voltage | V(VDDIO) = 1.71 to 1.89V; V(VDDIO) = VDD18 ±50 mV | GPIO[6:0], BISTEN | GND | 0.35 × V(VDDIO) |
V | ||
V(VDDIO) = 1.71 to 1.89V; V(VDDIO) = VDD18 ±50 mV | PDB, XIN/REFCLK, VDD_SEL |
GND | 0.63 | V | ||||
IIH | Input high current | VIN = V(VDDIO) = 1.71 to 1.89 V, | Internal pulldown enabled | GPIO[6:0], PDB, BISTEN | –100 | 100 | μA | |
IIH | Input high current | VIN = V(VDDIO) = 1.71 to 1.89 V, | Internal pulldown disabled | GPIO[6:0], XIN/REFCLK, VDD_SEL | –20 | 30 | μA | |
IIL | Input low current | VIN = 0V | GPIO[6:0], PDB, XIN/REFCLK, VDD_SEL, BISTEN | –20 | 30 | μA | ||
IOS | Output short circuit current | VOUT = 0 V | VOUT = 0 V | –25 | mA | |||
IOZ | TRI-STATE Output Current | VOUT = 0 V or VDDIO, PDB = L | VOUT = 0 V or VDDIO, PDB = L | –25 | 25 | μA | ||
3.3-V LVCMOS I/O | ||||||||
VOH | High level output voltage | IOH = –4 mA, V(VDDIO) = 3.0 to 3.6 V | GPIO[6:4], GPIO[2:0], LOCK, PASS | 2.4 | V(VDDIO) | V | ||
VOL | Low level output voltage | IOL = 4 mA, V(VDDIO) = 3.0 to 3.6 V | GPIO[6:0], LOCK, PASS | GND | 0.4 | V | ||
VIH | High level input voltage | V(VDDIO) = 3 to 3.6 V | GPIO[6:0], BISTEN | 2 | V(VDDIO) | V | ||
V(VDDIO) = 3 to 3.6 V | PDB, XIN/REFCLK, VDD_SEL |
1.17 | V(VDDIO) | |||||
VIL | Low level input voltage | V(VDDIO) = 3 to 3.6 V | GPIO[6:0], BISTEN | GND | 0.8 | V | ||
V(VDDIO) = 3 to 3.6 V | PDB, XIN/REFCLK, VDD_SEL |
GND | 0.63 | |||||
IIH | Input high current | VIN = 3 to 3.6 V, internal pulldown enabled | GPIO[6:0], PDB, BISTEN | –190 | 190 | μA | ||
VIN = 3 to 3.6 V, internal pulldown disabled | GPIO[6:0], XIN/REFCLK, VDD_SEL | –20 | 30 | μA | ||||
IIL | Input low current | VIN = 0 V | GPIO[6:0], PDB, XIN/REFCLK, VDD_SEL, BISTEN | –20 | 30 | μA | ||
IOS | Output short circuit current | VOUT = 0 V | GPIO[7:0], LOCK, PASS | –40 | mA | |||
IOZ | TRI-STATE output current | VOUT = 0 V or V(VDDIO), PDB = L | GPIO[7:0], LOCK, PASS | –25 | 35 | μA | ||
SERIAL CONTROL BUS1 | ||||||||
VIH | Input high level | I2C_SDA, I2C_SCL | 0.7 × V(I2C) | V(I2C) | V | |||
VIL | Input low level | GND | 0.3 × V(I2C) | V | ||||
VHY | Input hysteresis | 50 | mV | |||||
VOL | Output low level | Standard-mode/Fast-mode IOL = 3 mA | 0 | 0.4 | V | |||
Fast-mode Plus IOL = 20 mA | 0 | 0.4 | V | |||||
IIH | Input high current | VIN = V(I2C) | –10 | 10 | µA | |||
IIL | Input low current | VIN = 0V | –10 | 10 | µA | |||
CIN | Input capacitance | 5 | pF | |||||
V3LINK INPUT | ||||||||
VCM | Common mode voltage | RIN0+, RIN0- RIN1+, RIN1- |
1.2 | V | ||||
RT | Internal termination resistor | Single-ended | RIN0+, RIN1+ | 40 | 50 | 60 | Ω | |
Differential | RIN0+, RIN0- RIN1+, RIN1- |
80 | 100 | 120 | Ω | |||
V3LINK BIDIRECTIONAL CONTROL CHANNEL | ||||||||
VOUT-BC | Back Channel Output Single-ended voltage | RL = 50 Ω, coaxial configuration, forward channel disabled | RIN0+, RIN0- RIN1+, RIN1- |
190 | 225 | 260 | mV | |
VOD-BC | Back channel output differential | RL = 100 Ω, STP configuration, forward channel disabled | 380 | 450 | 520 | mV | ||
HSTX DRIVER |
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VCMTX | HS transmit static common-mode voltage | CSI_D3P/N, CSI_D2P/N, CSI_D1P/N, CSI_D0P/N, CSI_CLK1P/N, CSI_CLK0P/N | 150 | 200 | 250 | mV | ||
|ΔVCMTX(1,0)| | VCMTX mismatch when output is 1 or 0 | 5 | mVP-P | |||||
|VOD| | HS transmit differential voltage | 140 | 200 | 270 | mV | |||
|ΔVOD| | VOD mismatch when output is 1 or 0 | 14 | mV | |||||
VOHHS | HS output high voltage | 360 | mV | |||||
ZOS | Single-ended output impedance | 40 | 50 | 62.5 | Ω | |||
ΔZOS | Mismatch in single-ended output impedance | 10 | % | |||||
LPTX DRIVER |
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VOH | High level output voltage | Applicable when the supported data rate is ≤ 1.5 Gbps | CSI_D3P/N, CSI_D2P/N, CSI_D1P/N, CSI_D0P/N, CSI_CLK1P/N, CSI_CLK0P/N | 1.1 | 1.2 | 1.3 | V | |
Applicable when the supported data rate is > 1.5 Gbps | 0.95 | 1.3 | V | |||||
VOL | Low level output voltage | -50 | 50 | mV | ||||
ZOLP | Output impedance | 110 | Ω |