SNLS697A April 2021 – February 2023 TDES954
PRODUCTION DATA
The PDB pin is active HIGH and has internal 50 kΩ pull down resistor. PDB input must remain LOW while the VDD pin power supplies are in transition. Typically PDB will be connected to GPIO from processor also with internal pulldown. Alternatively, when VDD_SEL = LOW, an external RC network on the PDB pin may be connected to ensure PDB arrives after all the supply pins have settled to the recommended operating voltage. When PDB pin is pulled up to VDD18, a 10-kΩ pullup and a > 10-μF capacitor to GND are recommended to delay the PDB input signal rise. All inputs must not be driven until both power supplies have reached steady state. When VDD_SEL = HIGH it is not recommended to connect PDB through RC circuit as this may conflict with the sequencing of the external 1.1-V supply rail.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| PDB | ||||||
| tLRST | PDB Reset Low Pulse | 2 | 3 | ms | ||