SNLS697 Data sheet

SNLS697A April 2021 – February 2023 TDES954

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RGZ|48
- MPQF123F

Thermal pad, mechanical data (Package|Pins)

RGZ|48
- QFND014T

Orderable Information

7.4.1 CSI-2 Mode

When operating in CSI-2 V³Link input mode (with TSER953), the TDES954 receives CSI-2 formatted data on one or two V³Link input ports and forwards the data to the CSI-2 transmit port. The deserializer can operate in CSI-2 mode with synchronous back channel reference or non-synchronous mode. The forward channel line rate is independent of the CSI-2 rate in synchronous or non-synchronous with external clock mode. Each CSI-2 mode supports remapping of Virtual Channel IDs at the input of each receive port. This allows handling of conflicting VC-IDs for input streams from dual sensors and sending those streams to the same CSI-2 transmit port.

In CSI-2 mode each deserializer Rx Port can support a V³Link line rate up to 4.16 Gbps, where the forward channel and back channel rates are based on the reference frequency used for the serializer:

In Synchronous mode based on REFCLK input frequency reference, the V³Link line rate is a fixed value of 160 × REFCLK. V3LINK_PCLK = 4 × REFCLK and Back channel rate = 2 × REFCLK. For example with REFCLK = 25 MHz, line rate = 4.0 Gbps, V3LINK_PCLK = 100 MHz, back channel data rate = 50 Mbps. The sensor CSI-2 rate is independent of the line rate and Tx CSI-2 rate in synchronous clocking mode and can be up to 3.328 Gbps.
In Non-synchronous clocking mode, when the TSER953 uses external reference clock (f_CLKIN), the V³Link line rate is typically f_CLKIN × 80, V3LINK_PCLK = 2 × f_CLKIN or 1 x f_CLKIN and back channel data rate is set to 10 Mbps. For example, with f_CLKIN = 50 MHz, line rate = 4Gbps, V3LINK_PCLK = 100 MHz, and the back channel rate is 10 Mbps. The sensor CSI-2 rate is independent of the f_CLKIN.
In Non-synchronous clocking mode, when the TSER953 uses internal clock mode, the serializer uses the internal Always-on Clock (AON) as the reference clock for the forward channel. The OSCCLK_SEL select bit in the TSER953 must be asserted (0x05[3]=1) to enable maximum data rate when using internal clock mode, and the CLK_OUT function must be disabled. A separate reference is provided to the image sensor or ISP. The CSI-2 rate must be lower than the line rate. For example, with the internal clock of 24.2 MHz, the V³Link forward channel rate is 3.872 Gbps and the CSI-2 throughput must be ≤ 3.1 Gbps (See TSER953 datasheet for more information).