SLLSFJ8A december 2021 – june 2023 TDP0604
PRODUCTION DATA
The TDP0604 has the ability to slow down the TMDS output edge rates. In pin-strap mode the TX slew rate can not be controlled. In I2C mode both clock and data lanes slew rate can be controlled from a register. Table 8-10 shows the supported settings for each slew rate register based on HDMI data rate. The TDP0604 must be configured in limited redriver mode to control the TX slew rate.
HDMI Datarate | SLEW_CLK register | SLEW_3G register | SLEW_6G register |
---|---|---|---|
HDMI 1.4 | 3'b000 through 3'b011 | 3'b010 through 3'b101 | N/A |
HDMI 2.0 | 3'b000 through 3'b011 | N/A | 3'b011 through 3'b110 |