SLLSFI6A july 2022 – july 2023 TDP1204
PRODUCTION DATA
Table 8-23 lists the memory-mapped registers for the TDP1204 registers. All register offset addresses not listed in Table 8-23 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
8h | REV_ID | Revision ID | Go |
9h | PD_RST | Power Down and Reset control | Go |
Ah | MISC_CONTROL | Misc Control | Go |
Bh | GBL_SLEW_CTRL | Global TX Slew control for data lanes in HDMI1.4 and 2.0 | Go |
Ch | GBL_SLEW_CTRL2 | Global TX Slew control for data and clock | Go |
Dh | GBL_CTRL1 | Global control | Go |
Eh | GBL_CTLE_CTRL | Global CTLE control | Go |
10h | DDC_CFG | DDC Buffer controls | Go |
11h | LANE_ENABLE | Lane enables | Go |
12h | CLK_CONFIG1 | CLK lane TX swing and FFE control | Go |
13h | CLK_CONFIG2 | CLK lane RX EQ control | Go |
14h | D0_CONFIG1 | D0 lane TX swing and FFE control | Go |
15h | D0_CONFIG2 | D0 lane RX EQ control | Go |
16h | D1_CONFIG1 | D1 lane TX swing and FFE control | Go |
17h | D1_CONFIG2 | D1 lane RX EQ control | Go |
18h | D2_CONFIG1 | D2 lane TX swing and FFE control | Go |
19h | D2_CONFIG2 | D2 lane RX EQ control | Go |
1Ah | SIGDET_TH_CFG | SIGDET voltage threshold control | Go |
1Ch | GBL_STATUS | Global Powerdown and Standby Status | Go |
1Dh | AEQ_CONTROL1 | Adaptive EQ control1 | Go |
1Eh | AEQ_CONTROL2 | Adaptive EQ control2 | Go |
20h | SCDC_TMDS_CONFIG | SCDC TMDS Clock Ratio | Go |
31h | SCDC_SINK_CONFIG | SCDC SNK FRL FFE and Rate | Go |
35h | SCDC_SRC_TEST | SCDC Test | Go |
41h | SCDC_STATUS10 | Lanes 0 and 1 FRL Training Status | Go |
42h | SCDC_STATUS32 | Lanes 2 and 3 FRL Training Status | Go |
50h | AEQ_STATUS | Adaptive EQ Status | Go |
51h | AEQ_STATUS2 | Adaptive EQ Status | Go |
Complex bit access types are encoded to fit into small table cells. Table 8-24 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
H | H | Set or cleared by hardware |
R | R | Read |
RH | R H | Read Set or cleared by hardware |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
WtoP | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
REV_ID is shown in Table 8-25.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | REV_ID | RH | 3h | Device revision. |
PD_RST is shown in Table 8-26.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SOFT_RST | HWtoP | 0h | Writing a 1 to this field resets all fields |
6 | SCDC_SOFT_RST | HWtoP | 0h | Writing a 1 to this field resets the fields in the SCDC registers 20h, 31h, 35h, 41h and 42h. |
5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | HPD_PWRDWN_DISABLE | R/W | 0h | Mode to ignore HPD pin and always enter active state unless PD_EN is high
0h = Automatically enter power down based on HPD_IN 1h = Always remain in active state or Standby |
1 | STANDBY_DISABLE | R/W | 0h | When high, Standby state is disabled and the device will immediately enter active mode with all lanes enabled when not in power down.
When low, the device will enter Standby state when exiting power down and wait for incoming data before entering active mode.
0h = Standby state enabled 1h = Standby state disabled |
0 | PD_EN | R/W | 1h | I2C power down. Software should clear this field after it has completed initialization. HPD_OUT will be asserted low when this field is set.
0h = Normal operation 1h = Forced power down by I2C |
MISC_CONTROL is shown in Table 8-27.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | LANE_SWAP | R/W | 0h | This field swaps the input and output lanes.
0h = No lanes swapped 1h = Both input and output lanes swapped |
6 | RESERVED | R/W | 0h | Reserved |
5 | RX_TERM_DISABLE | R/W | 0h | When set will disable Rx termination.
0h = Enabled when HPD_IN high. 1h = Disable |
4 | HPD_OUT_SEL | R/W | 0h | Selects whether HPD_OUT is push/pull or open-drain.
0h = Push Pull 1h = Open Drain |
3 | EQ_SNOOP_CTRL | R/W | 1h | Control whether Rx EQ is adjusted in response to snooped TXFFE when TXFFE snooping is enabled through registers 41h and 42h.
0h = Rx EQ automatically adjusted for TXFFE 1h = Rx EQ is fixed |
2 | RATE_SNOOP_CTRL | R/W | 0h | Control snooping of HDMI rates. When snooping is disabled, correct HDMI rate must be written through I2C to registers 20h and 31h.
0h = Snooping enabled 1h = Snooping disabled |
1-0 | TXFFE_SNOOP_CTRL | R/W | 0h | Control snooping of TXFFE
0h = DDC snooping through registers 35h, 41h and 42h 1h = DDC snooping disabled. TXFFE controlled through I2C writes to 35h, 41h and 42h 2h = DDC snooping disabled. TXFFE controlled through writes to CLK_TXFFE, D0_TXFFE, D1_TXFFE, and D2_TXFFE 3h = DDC snooping disabled. TXFFE controlled through writes to CLK_TXFFE, D0_TXFFE, D1_TXFFE, and D2_TXFFE |
GBL_SLEW_CTRL is shown in Table 8-28.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-4 | SLEW_3G | R/W | 3h | Field controls slew rate for HDMI 1.4 data lane and HDMI 2.1 3 Gbps FRL data
lanes. 0h = slowest edge rate 7h = fastest edge rate |
3 | RESERVED | R | 0h | Reserved |
2-0 | SLEW_6G | R/W | 4h | Field controls slew rate for HDMI 2.0 data lanes and HDMI 2.1 6 Gbps FRL data
lanes. 0h = slowest edge rate 7h = fastest edge rate |
GBL_SLEW_CTRL2 is shown in Table 8-29.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-4 | SLEW_8G10G12G | R/W | 7h | Field controls slew rate for data lanes for 8 Gbps, 10 Gbps and 12 Gbps FRL
datarates 0h = slowest edge rate 7h = fastest edge rate |
3 | RESERVED | R | 0h | Reserved |
2-0 | SLEW_CLK | R/W | 1h | Field control slew rate of clock lane in HDMI 1.4b and HDMI 2.0 modes.
0h = slowest edge rate 7h = fastest edge rate |
GBL_CTRL1 is shown in Table 8-30.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | GLOBAL_LINR_EN | R/W | 0h | Global control for selecting between linear redriver or limited redriver.
0h = Limited 1h = Linear |
6 | TX_AC_EN | R/W | 0h | Controls selection of ac-coupled or dc-coupled TX termination. When AC-coupled is enabled, 50 Ω termination on both P and N to VCC will be enabled.
0h = dc-coupled 1h = ac-coupled |
5-4 | GLOBAL_DCG | R/W | 2h | CTLE DCGain for all lane. 0h = −3 dB 1h = −3 dB 2h = 0 dB 3h = +1 dB |
3 | TXTERM_AUTO_HDMI14 | R/W | 0h | Selects between no termination and 300 Ωs when TERM = 2h and operating in
HDMI1.4. 0h = No termination for clock less than or equal to 165 MHz and 300 Ω for clock greater than 225 MHz 1h = 300 Ω |
2 | CTLEBYP_EN | R/W | 0h | Selects whether or not CTLE bypass is enabled or not when GLOBAL_DCG is set to 2h and EQ set to 0h.
0h = CTLE bypass disabled 1h = CTLE bypass enabled |
1-0 | TERM | R/W | 2h | TX termination control
0h = No termination 1h = 300 Ω 2h = Automatic based HDMI mode 3h = 100 Ω |
GBL_CTLE_CTRL is shown in Table 8-31.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | GLOBAL_CTLEBW | R/W | 0h | CTLE bandwidth control. 0 is lowest and 3h is highest. |
5-4 | HDMI14_CTLE_SEL | R/W | 3h | Selects the CTLE used when datarate is HDMI 1.4. Value programmed into this field
will apply to data lanes only. Clock lane will always use 3 Gbps
CTLE. 0h = 3 Gbps CTLE 1h = 6 Gbps CTLE 2h = Auto select based on snoop datarate 3h = 12 Gbps CTLE |
3-2 | HDMI20_CTLE_SEL | R/W | 3h | Selects the CTLE used when datarate is HDMI 2.0. Value programmed into this field
will apply to data lanes only. Clock lane will always use 3 Gbps
CTLE. 0h = 3 Gbps CTLE 1h = 6 Gbps CTLE 2h = Auto select based on snoop datarate 3h = 12 Gbps CTLE |
1-0 | HDMI21_CTLE_SEL | R/W | 3h | Selects the CTLE used when datarate is HDMI 2.1. Value programmed into this field will apply to all four lanes.
0h = 3 Gbps CTLE 1h = 6 Gbps CTLE 2h = Auto select based on snoop datarate 3h = 12 Gbps CTLE |
DDC_CFG is shown in Table 8-32.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | RESERVED | R | 0h | Reserved |
1 | DDC_LV_DCC_EN | R/W | 1h | Controls whether duty cycle correction is enabled for DDC LV side.
0h = DCC disabled 1h = DCC enabled |
0 | DDCBUF_EN | R/W | 0h | Controls whether or not DDC buffer is enabled. Regardless of the state of this field, the device will always disable the DDC buffer anytime HPD_IN is low or when PD_EN field is 1.
0h = DDC Buffer Disabled 1h = DDC Buffer Enabled |
LANE_ENABLE is shown in Table 8-33.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | HDMI20_VOD | R/W | 1h | VOD control for limited redriver in HDMI 2.0 0h = Use values in CLK_VOD, D0_VOD, D1_VOD and D2_VOD 1h = Default (1000 mV) 2h = Default − 5% 3h = Default + 5% |
5-4 | HDMI14_VOD | R/W | 1h | VOD control for limited redriver in HDMI 1.4 0h = Use values in CLK_VOD, D0_VOD, D1_VOD and D2_VOD 1h = Default (1000 mV) 2h = Default − 5% 3h = Default − 10% |
3 | CLK_LANE_EN | R/W | 1h | Enable for CLK lane
0h = Disabled 1h = Enabled |
2 | D0_LANE_EN | R/W | 1h | Enable for D0 lane
0h = Disabled 1h = Enabled |
1 | D1_LANE_EN | R/W | 1h | Enable for D0 lane
0h = Disabled 1h = Enabled |
0 | D2_LANE_EN | R/W | 1h | Enable for D0 lane
0h = Disabled 1h = Enabled |
CLK_CONFIG1 is shown in Table 8-34.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-4 | CLK_TXFFE | R/W | 0h | TXFFE control for CLK lane. This field is only honored in HDMI 2.1. 0h = 0.0 dB 1h = 3.5 dB 2h = 6.0 dB 3h = Reserved 4h = −1.5 dB 5h = −2.5 dB 6h = −3.5 dB 7h = −4.8 dB |
3 | RESERVED | R | 0h | Reserved |
2-0 | CLK_VOD | R/W | 3h | Differential Swing control for CLK lane. 0h = Limited −15% Linear 800 mV 1h = Limited −10% Linear 900 mV 2h = Limited − 5% Linear 1000 mV 3h = Limited 800 mV Linear 1200 mV 4h = Limited +5% Linear Reserved 5h = Limited +10% Linear Reserved 6h = Limited +15% Linear Reserved 7h = Limited +20% Linear Reserved |
CLK_CONFIG2 is shown in Table 8-35.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | R | 0h | Reserved |
3-0 | CLK_EQ | R/W | 0h | EQ control for CLK lane. This field is only honored in HDMI 2.1.
0h = Min EQ Fh = Max EQ |
D0_CONFIG1 is shown in Table 8-36.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-4 | D0_TXFFE | R/W | 0h | TXFFE control for D0 lane. 0h = 0.0 dB 1h = 3.5 dB 2h = 6.0 dB 3h = Reserved 4h = −1.5 dB 5h = −2.5 dB 6h = −3.5 dB 7h = −4.8 dB |
3 | RESERVED | R | 0h | Reserved |
2-0 | D0_VOD | R/W | 3h | Differential Swing control for D0 lane. 0h = Limited −15% Linear 800 mV 1h = Limited −10% Linear 900 mV 2h = Limited - 5% Linear 1000 mV 3h = Limited 1000 mV Linear 1200 mV 4h = Limited +5% Linear Reserved 5h = Limited +10% Linear Reserved 6h = Limited +15% Linear Reserved 7h = Limited +20% Linear Reserved |
D0_CONFIG2 is shown in Table 8-37.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | R | 0h | Reserved |
3-0 | D0_EQ | R/W | 0h | EQ control for D0 lane.
0h = Min EQ Fh = Max EQ |
D1_CONFIG1 is shown in Table 8-38.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-4 | D1_TXFFE | R/W | 0h | TXFFE control for D1 lane. 0h = 0.0 dB 1h = 3.5 dB 2h = 6.0 dB 3h = Reserved 4h = −1.5 dB 5h = −2.5 dB 6h = −3.5 dB 7h = −4.8 dB |
3 | RESERVED | R | 0h | Reserved |
2-0 | D1_VOD | R/W | 3h | Differential Swing control for D1 lane. 0h = Limited −15% Linear 800 mV 1h = Limited −10% Linear 900 mV 2h = Limited − 5% Linear 1000 mV 3h = Limited 1000 mV Linear 1200 mV 4h = Limited +5% Linear Reserved 5h = Limited +10% Linear Reserved 6h = Limited +15% Linear Reserved 7h = Limited +20% Linear Reserved |
D1_CONFIG2 is shown in Table 8-39.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | R | 0h | Reserved |
3-0 | D1_EQ | R/W | 0h | EQ control for D1 lane
0h = Min EQ Fh = Max EQ |
D2_CONFIG1 is shown in Table 8-40.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-4 | D2_TXFFE | R/W | 0h | TXFFE control for D2 lane 0h = 0.0 dB 1h = 3.5 dB 2h = 6.0 dB 3h = Reserved 4h = −1.5 dB 5h = −2.5 dB 6h = −3.5 dB 7h = −4.8 dB |
3 | RESERVED | R | 0h | Reserved |
2-0 | D2_VOD | R/W | 3h | Differential Swing control for D2 lane. 0h = Limited −15% Linear 800 mV 1h = Limited -10% Linear 900 mV 2h = Limited - 5% Linear 1000 mV 3h = Limited 1000 mV Linear 1200 mV 4h = Limited +5% Linear Reserved 5h = Limited +10% Linear Reserved 6h = Limited +15% Linear Reserved 7h = Limited +20% Linear Reserved |
D2_CONFIG2 is shown in Table 8-41.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | R | 0h | Reserved |
3-0 | D2_EQ | R/W | 0h | EQ control for D2 lane.
0h = Min EQ Fh = Max EQ |
SIGDET_TH_CFG is shown in Table 8-42.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-4 | CFG_SIGDET_HYST | R/W | 4h | Controls the SIGDET hysteresis. Value programmed into this field plus value
programmed into CFG_SIGDET_VTH field defines the SIGDET assert
threshold. 0h = 0 mV 1h = 12 mV 2h = 25 mV 3h = 37 mV 4h = 55 mV 5h = 63 mV 6h = 75 mV 7h = 90 mV |
3 | RESERVED | R | 0h | Reserved |
2-0 | CFG_SIGDET_VTH | R/W | 4h | Controls the SIGDET de-assert voltage threshold. 0h = 58 mV 1h = 60 mV 2h = 72 mV 3h = 84 mV 4h = 95 mV 5h = 108 mV 6h = 120 mV 7h = 135 mV |
GBL_STATUS is shown in Table 8-43.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PD_STATUS | RH | 0h | Power Down status |
6 | STANDBY_STATUS | RH | 0h | Standby Status |
5-0 | RESERVED | R | 0h | Reserved |
AEQ_CONTROL1 is shown in Table 8-44.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | FULLAEQ_UPPER_EQ | R/W | Fh | Maximum EQ value to check for full AEQ mode |
3-2 | AEQ_PATTERN_CTRL | R/W | 0h | Control how link training pattern snooping for EQ adaptation
0h = Require a read of pattern register 41h/42h after a rate change. Allow eq adaptation for patterns 0, 5, 6, 7, and 8. 1h = Require a read of pattern register 41h/42h after a rate change. Allow eq adaptation for patterns 5, 6, 7, and 8. 2h = Allow eq adaptation for patterns 0, 5, 6, 7, and 8. No need for read after rate change 3h = Allow eq adaptation for patterns 5, 6, 7, and 8. No need for read after rate change. |
1 | AEQ_START_CTRL | R/W | 1h | Control whether starts based on signal detect or both signal detect and FLT_UPDATE cleared
0h = Only require signal detect 1h = Require signal detect and clearing of FLT_UPDATE |
0 | AEQ_TX_DELAY_EN | R/W | 1h | Control whether TX remains disabled during EQ adaptation
0h = TX active during adaptation 1h = TX disabled during adaptation |
AEQ_CONTROL2 is shown in Table 8-45.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | AEQ_MODE | R/W | 0h | Selects between two Adaption modes
0h = AEQ with hits counted at mideye for every EQ. 1h = AEQ with hits counted at mideye only for EQ equal 0. |
6 | AEQ_EN | R/W | 0h | Controls whether or not adaptive EQ is enabled.
0h = AEQ disabled 1h = AEQ enabled |
5-4 | RESERVED | R/W | 0h | Reserved |
3 | OVER_EQ_SIGN | R/W | 0h | Selects the sign for OVER_EQ_CTRL field.
0h = positive 1h = negative |
2-0 | OVER_EQ_CTRL | R/W | 0h | This field will increase or decrease the AEQ by value programmed into this field.
For example, full AEQ value is 6 and this field is programmed to 2
and OVER_EQ_SIGN = 0, then EQ value used will be 8. This field is
only used in Full AEQ mode. 0h = 0 or −8 1h = 1 or −7 2h = 2 or −6 3h = 3 or −5 4h = 4 or −4 5h = 5 or −3 6h = 6 or −2 7h = 7 or −1 |
SCDC_TMDS_CONFIG is shown in Table 8-46.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | RESERVED | R | 0h | Reserved |
1 | TMDS_CLK_RATIO | RH/W | 0h | TMDS Bit Period to TMDS Clock Period Ratio. Reads last value snooped through DDC read/write or I2C write.
0h = 1/10 (HDMI 1.4b) 1h = 1/40 (HDMI 2.0) |
0 | RESERVED | R | 0h | Reserved |
SCDC_SINK_CONFIG is shown in Table 8-47.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | FFE_LEVELS | RH/W | 0h | Indicates the maximum TXFFE level supported for the current FRL rate. Read last value snooped through DDC read/write or I2C write.
0h = Only TXFFE0 supported 1h = TXFFE0-1 supported 2h = TXFFE0-2 supported 3h = TXFFE0-3 supported |
3-0 | FRL_RATE | RH/W | 0h | Selects FRL rate and lane count. Read last value snooped through DDC read/write or I2C write.
0h = Disable FRL 1h = 3 Gbps on 3 lanes 2h = 6 Gbps on 3 lanes 3h = 6 Gbps on 4 lanes 4h = 8 Gbps on 4 lanes 5h = 10 Gbps on 4 lanes 6h = 12 Gbps on 4 lanes |
SCDC_SRC_TEST is shown in Table 8-48.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | Reserved |
5 | FLT_NO_TIMEOUT | RH/W | 0h | Set by sink test equipment to have source not time out during FRL link training
0h = Normal operation 1h = Source does not timeout |
4 | RESERVED | R | 0h | Reserved |
3 | TX_NO_FFE | RH/W | 0h | Test mode to disable FFE. Read last value snooped through DDC read/write or I2C write.
0h = Normal TXFFE 1h = TX sent with no FFE |
2 | TX_DEEMPH_ONLY | RH/W | 0h | Test mode to enable de-emphasis only. Read last value snooped through DDC read/write or I2C write.
0h = Normal TXFFE 1h = TX sent de-emphasis only |
1 | TX_PRESHOOT_ONLY | RH/W | 0h | Test mode to enable pre-shoot only. Read last value snooped through DDC read/write or I2C write.
0h = Normal TXFFE 1h = TX sent with pre-shoot only |
0 | RESERVED | R | 0h | Reserved |
SCDC_STATUS10 is shown in Table 8-49.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | LN1_LTP_REQ | RH/W | 0h | Link training pattern request for lane 1. Reads last value read through DDC or written through I2C. A DDC read/I2C write of Eh advances the current FFE level for this lane saturating at the value of FFE_LEVELS. A DDC read/I2C write of Fh clears for FFE level for all lanes to TXFFE0. |
3-0 | LN0_LTP_REQ | RH/W | 0h | Link training pattern request for lane 0. Reads last value read through DDC or written through I2C. A DDC read/I2C write of Eh advances the current FFE level for this lane saturating at the value of FFE_LEVELS. A DDC read/I2C write of Fh clears for FFE level for all lanes to TXFFE0. |
SCDC_STATUS32 is shown in Table 8-50.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | LN3_LTP_REQ | RH/W | 0h | Link training pattern request for lane 3. Reads last value read through DDC or written through I2C. A DDC read/I2C write of Eh advances the current FFE level for this lane saturating at the value of FFE_LEVELS. A DDC read/I2C write of Fh clears for FFE level for all lanes to TXFFE0. |
3-0 | LN2_LTP_REQ | RH/W | 0h | Link training pattern request for lane 2. Reads last value read through DDC or written through I2C. A DDC read/I2C write of Eh advances the current FFE level for this lane saturating at the value of FFE_LEVELS. A DDC read/I2C write of Fh clears for FFE level for all lanes to TXFFE0. |
AEQ_STATUS is shown in Table 8-51.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | AEQDONE_STAT | RH | 1h | This field is low while AEQ is active and high when it is done. It is valid when FRL training and AEQ_EN = 1 or when FORCE_AEQ_EN = 1 and HW has reset FORCE_AEQ back to 0.
0h = AEQ is running 1h = AEQ is done |
6 | AEQ_HC_OVERFLOW | RH | 0h | 13-bit AEQ hit counter overflow status |
5 | RESERVED | R | 0h | Reserved |
4 | RXD1_DONE_STAT | RH | 0h | This flag is set after DAC wait timer expires. |
3-0 | RXD1_AEQ_STAT | RH | 0h | Optimal EQ determined by FSM after the completion of Full AEQ. This field will include the value programmed into OVER_EQ_CTRL field. |
AEQ_STATUS2 is shown in Table 8-52.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-4 | VOD_RANGE_STAT | RH | 0h | VOD range selected by the last AEQ run |
3-0 | AEQ_EYE_STAT | RH | 0h | EYE status from the last AEQ run. Relative to the maximum limit of 15. |