The TDP1204 has a DDC buffer for capacitance isolation and for shifting 5-V levels present on the HDMI connector to as low as 1.2-V levels on the GPU source side. The HV_DDC_SDA and HV_DDC_SCL pins support 5-V levels while the LV_DDC_SDA and LV_DDC_SCL pins support 1.2-V, 1.8-V, and 3.3-V levels. When the DDC buffer is used in source application, the HV side must be pulled up using 1.5-kΩ to 2-kΩ resistors. It is recommended to use 1.8-kΩ ±5% resistor. HV_DDC_SDA and HV_DDC_SCL pins will typically be pulled up to HDMI 5-V. The LV_DDC_SDA and LV_DDC_SCL are internally pulled up to VIO.

The TDP1204 enables DDC translation from low voltage (system side) voltage levels to 5-V (HDMI cable side) voltage levels without degradation of system performance. The TDP1204 contains 2 bidirectional, open-drain buffers specifically designed to support up and down-translation between the low voltage (LV) side DDC-bus and the high voltage (HV) 5-V DDC-bus. The HV I/Os (HV_DDC_SCL and HV_DDC_SDA) are overvoltage tolerant to 5.5-V. After HPD_IN high, a LOW level on LV side (below VILC = 0.08 × VIO) turns the corresponding HV driver (either SDA or SCL) on and drives HV side down to V_HVOL. When LV side rises above approximately 0.10 × VIO, the HV pulldown driver is turned off and the internal pullup resistor pulls the pin HIGH. When HV side falls first and goes below 1.6-V, a CMOS hysteresis input buffer detects the falling edge, turns on the LV driver, and pulls LV down to approximately V_LVOL = 0.16 × VIO. The LV side pulldown is not enabled unless the LV voltage goes below VILC. If the LV side low voltage goes below VILC, the HV side pulldown driver is enabled until LV side rises above (VILC + ΔVT-HYST), then HV side, if not externally driven LOW, continues to rise being pulled up by the external pullup resistor.

Figure 8-4 DDC Buffer Block Diagram

Figure 8-5 shows the connection of the LV and HV DDC pins when using the DDC buffer. This connection is supported in pin-strap mode when MODE pin is "0" or "1". In I2C mode, the DDCBUF_EN register must be set to enable the DDC Buffer.

Figure 8-5 Source Application: DDC Buffer Enabled

Figure 8-6 shows an example source application of snooping from the HV DDC pins. In this example, the DDC buffer must be enabled and the LV DDC pins must be floating. This connection is supported in pin-strap mode when MODE pin is "0" or "1". In I2C mode, the DDCBUF_EN register must be set to enable the DDC Buffer.

Figure 8-6 Source Application: DDC Buffer Enabled and Snoop from HV DDC pins

Figure 8-7 shows an example source application of snooping from the LV DDC pins. In this example, the DDC buffer must be disabled and the HV DDC pins must be floating. This connection is supported in pin-strap mode when MODE pin is "R". In I2C mode, the DDCBUF_EN register must be cleared to disable the DDC Buffer.

Figure 8-7 Source Application: DDC Buffer Disabled and Snoop from LV DDC pins

Figure 8-8 shows the connection of the LV and HV DDC pins when using the DDC buffer in a sink application. This connection is supported in pin-strap mode when MODE pin is "0" or "1". In I2C mode, the DDCBUF_EN register must be set to enable the DDC Buffer.

Figure 8-8 Sink Application: DDC Buffer Enabled

Figure 8-9 shows an example sink application of snooping from the LV DDC pins. In this example, the DDC buffer must be disabled and the HV DDC pins must be floating. This connection is supported in pin-strap mode when MODE pin is "R". In I2C mode, the DDCBUF_EN register must be cleared to disable the DDC Buffer.

Figure 8-9 Sink Application: DDC Buffer Disabled and Snoop from LV DDC pins

Figure 8-10 shows an example sink application of snooping from the HV DDC pins. In this example, the DDC buffer must be enabled and the LV DDC pins must be floating. This connection is supported in pin-strap mode when MODE pin is "0" or "1". In I2C mode, the DDCBUF_EN register must be set to enable the DDC Buffer.

Figure 8-10 Sink Application: DDC Buffer Enable and Snoop from HV DDC pins