SLLSFI6A july 2022 – july 2023 TDP1204
PRODUCTION DATA
In I2C mode, all settings of the TDP1204 can be controlled through the registers. The TDP1204 7-bit I2C address is determined by the ADDR/EQ0 pin. All other 4-level and 2-level pins are not used in I2C mode since the functions exist in a register. The SCL/CFG0 pin will function as the I2C clock and the SDA/CFG1 pin will function as the I2C data.
The TDP1204 defaults to power down in I2C mode. Upon completion of initialization of the TDP1204, software must clear the PD_EN field to exit the power down state. The HPD_OUT pin will be asserted low while the PD_EN register is set.
The TDP1204 supports 1.2-V, 1.8-V, and 3.3-V I2C signaling levels. Selection of 1.2-V, 1.8-V, or 3.3-V is determined by the VIO pin as provided in Table 8-2.