SLLSFI6A july   2022  – july 2023 TDP1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  4-Level Inputs
      2. 8.2.2  I/O Voltage Level Selection
      3. 8.2.3  HPD_OUT
      4. 8.2.4  Lane Control
      5. 8.2.5  Swap
      6. 8.2.6  Linear and Limited Redriver
      7. 8.2.7  Main Link Inputs
      8. 8.2.8  Receiver Equalizer
      9. 8.2.9  CTLE Bypass
      10. 8.2.10 Adaptive Equalization in HDMI 2.1 FRL
        1. 8.2.10.1 HDMI 2.1 TX Compliance Testing with AEQ Enabled
      11. 8.2.11 HDMI 2.1 Link Training Compatible Rx EQ
      12. 8.2.12 Input Signal Detect
      13. 8.2.13 Main Link Outputs
        1. 8.2.13.1 Transmitter Bias
        2. 8.2.13.2 Transmitter Impedance Control
        3. 8.2.13.3 TX Slew Rate Control
        4. 8.2.13.4 TX Pre-Emphasis and De-Emphasis Control
        5. 8.2.13.5 TX Swing Control
      14. 8.2.14 DDC Buffer
      15. 8.2.15 HDMI DDC Capacitance
      16. 8.2.16 DisplayPort
    3. 8.3 Device Functional Modes
      1. 8.3.1 MODE Control
        1. 8.3.1.1 I2C Mode (MODE = "F")
        2. 8.3.1.2 Pin Strap Modes
          1. 8.3.1.2.1 Pin-Strap: HDMI 1.4 and HDMI 2.0 Functional Description
          2. 8.3.1.2.2 Pin-Strap HDMI 2.1 Function (MODE = "0"): Fixed Rx EQ and DDC Buffer Enabled
          3. 8.3.1.2.3 Pin-Strap HDMI 2.1 Function (MODE = "1"): Flexible RX EQ and DDC Buffer Enabled
          4. 8.3.1.2.4 Pin-Strap HDMI 2.1 Function (MODE = "R"): Flexible Rx EQ and DDC Buffer Disabled
      2. 8.3.2 DDC Snoop Feature
        1. 8.3.2.1 HDMI Type
        2. 8.3.2.2 HDMI 2.1 FRL Snoop
      3. 8.3.3 Low Power States
    4. 8.4 Programming
      1. 8.4.1 Pseudocode Examples
        1. 8.4.1.1 HDMI 2.1 Source Example with DDC Snoop and DDC Buffer Enabled
        2. 8.4.1.2 HDMI 2.1 Source Example with DDC Snoop Disabled and DDC Buffer Disabled
      2. 8.4.2 TDP1204 I2C Address Options
      3. 8.4.3 I2C Target Behavior
    5. 8.5 Register Maps
      1. 8.5.1 TDP1204 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Source-Side Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Pre-Channel (LAB)
        2. 9.2.2.2 Post-Channel (LCD)
        3. 9.2.2.3 Common Mode Choke
        4. 9.2.2.4 ESD Protection
      3. 9.2.3 Application Curves
    3. 9.3 Typical Sink-Side Application
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedures
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Supply Decoupling
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over recommended voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
PACTIVE-H14-LT-ARX-DTX Power dissipation in HDMI 1.4 3.4 Gbps active operation Pin Strap mode; DR = 3.4 Gbps; HPD_IN = H; No de-emphasis/pre-emphasis; Limited redriver mode; DC-coupled TX; AC-coupled RX; 3 Gbps CTLE; 190 265 mW
PACTIVE-H20-LT-ARX-DTX Power dissipation in HDMI 2.0 6 Gbps active operation Pin Strap mode; DR = 6 Gbps; HPD_IN = H; No de-emphasis/pre-emphasis; Limited redriver mode; DC-coupled TX; AC-coupled RX; 6 Gbps CTLE; 215 305 mW
PACTIVE-FRL-LT-ARX-ATX Power dissipation in FRL 12 Gbps active operation when TX is AC-coupled (AC_EN = H) Pin Strap mode; DR = 12 Gbps; HPD_IN = H; TXFFE0; Limited redriver mode; AC-coupled TX; AC-coupled RX;12 Gbps CTLE; 840 1220 mW
PACTIVE-FRL-LT-ARX-DTX Power dissipation in FRL 12 Gbps active operation when TX is DC-coupled (AC_EN = L) Pin Strap mode; DR = 12 Gbps; HPD_IN = H; TXFFE0; Limited redriver mode; DC-coupled TX; AC-coupled RX; 12 Gbps CTLE; 575 785 mW
PACTIVE-FRL-LR-ARX-DTX Power dissipation in FRL 12 Gbps active operation when TX is DC-coupled (AC_EN = L) Pin Strap mode; DR = 12 Gbps; HPD_IN = H; Highest linearity setting; Linear redriver mode; DC-coupled TX; AC-coupled RX; 12 Gbps CTLE; 220 310 mW
PACTIVE-FRL-LR-ARX-ATX Power dissipation in FRL 12 Gbps active operation when TX is AC-coupled (AC_EN = H) Pin Strap mode; DR = 12 Gbps; HPD_IN = H; Highest linearity setting; Linear redriver mode; AC-coupled TX; AC-coupled RX; 12 Gbps CTLE 660 990 mW
PPD Power in power-down (HPD_IN = L) Pin Strap mode; HPD_IN = L; EN = L or H; High-speed outputs are disconnected; 0.6 2 mW
PSD Power in standby (HPD_IN = H) but no incoming signal with DDC Buffer disabled Pin Strap mode; HPD_IN = H; No incoming signal; EN = H; DC-coupled TX; AC-coupled RX; Limited redriver mode; High-speed outputs are connected; 1.0 1.85 mW
PSD Power in standby (HPD_IN = H) but no incoming signal with DDC buffer enabled. Pin Strap mode; HPD_IN = H; No incoming signal; EN = H; DC-coupled TX; AC-coupled RX; Limited redriver mode; High-speed outputs are connected; 1.2 2.05 mW
IVIOQ VIO quiescent current HPD_IN = H;VCC = VIO = 3.6 V; LV_DDC_SDA/SCL = H; HV_DDC_SDA/SCL = H; 16 µA
IVIOA VIO active instantaneous current VCC = VIO = 3.6 V; HPD_IN = H; 1 mA
2-LEVEL CONTROL PINS (EN, SCL/CFG0, SDA/CFG1, AC_EN, HPDOUT_SEL)
VIO_TRSHD Threshold for selecting between 1.2-V LVCMOS / 1.8-V LVCMOS 1.5 V
VIO_TRSHD Threshold for selecting between 1.8-V LVCMOS / 3.3-V LVCMOS 2.5 V
VIL_1p2V Low-level input voltage for SCL/CFG0, SDA/CFG1 VIO = 1.26 V; VCC = 3.0 V; -0.3 0.378 V
VIH_1p2V High-level input voltage for SCL/CFG0, SDA/CFG1 VIO = 1.14 V; VCC = 3.6 V; 0.8 3.6 V
VIL_1p8V Low-level input voltage  for SCL/CFG0, SDA/CFG1 VIO = 1.9 V; VCC = 3.0 V; -0.3 0.57 V
VIH_1p8V High-level input voltage for SCL/CFG0, SDA/CFG1 VIO = 1.7 V; VCC = 3.6 V; 1.19 3.6 V
VIL_3p3V Low-level input voltage for SCL/CFG0, SDA/CFG1 VIO = 3.6 V; VCC = 3.0 V; -0.3 0.8 V
VIL_3p3V Low-level input voltage for AC_EN, HPDOUT_SEL VIO = 3.6 V; VCC = 3.0 V; -0.3 0.8 V
VIH_3p3V High-level input voltage for SCL/CFG0, SDA/CFG1 VIO = 3.0 V; VCC = 3.6 V; 2.2 3.6 V
VIH_3p3V High-level input voltage for AC_EN, HPDOUT_SEL VIO = 3.0 V; VCC = 3.6 V; 2.2 3.6 V
VOL_1p2V Low-level output voltage SDA/CFG1 VCC = 3.0 V; VIO = 1.2 V; -0.3 0.3 V
IOL_1p2V Low-level output current SDA/CFG1 VCC = 3.0 V; VIO = 1.2 V; 2 mA
VOL Low-level output voltage SDA/CFG1 VCC = 3.0 V; VIO = 1.8 V or 3.3 V; -0.3 0.4 V
IOL Low-level output current SDA/CFG1 VCC = 3.0 V; VIO = 1.8 V or 3.3 V; 4 mA
IIL_I2C Low-level input current SCL/CFG0, SDA/CFG1 VIN = 0 V; VIO = 1.8 V or 3.3 V; –1 1 µA
ILEAK Fail-safe input current for SCL/CFG0, SDA/CFG1 VIN = 3.6 V; VCC = 0 V; –25 25 µA
VIL_EN Low-level input voltage for EN pin. VIO = 1.14 V; VCC = 3.3 V; -0.3 0.4 V
VIH_EN High-level input voltage for EN pin. VIO = 3.6 V; VCC = 3.3 V; 0.8 3.6 V
IIL Low-level input current EN VIN = 0 V; VIO = 1.8 V or 3.3 V; VCC = 3.6 V –20 20 µA
IIL Low-level input current AC_EN, HPDOUT_SEL VIN = 0 V; VIO = 1.8 V or 3.3 V; –1 1 µA
IIH_EN High-level input current for EN VIN = 3.6 V; VIO = 1.8 V or 3.3 V; –1 1 µA
IIH_ACEN High-level input current for AC_EN VIN = 3.6 V; VIO = 1.8 V or 3.3 V; –24 24 µA
IIH_HPDOUTSEL High-level input current for HPDOUT_SEL VIN = 3.6 V; VIO = 1.8 V or 3.3 V; –24 30 µA
RPU_EN Internal Pull-up resistance on EN. 125 250 350 kΩ
RPD_ACEN Internal Pull-down resistance on AC_EN 125 250 350 kΩ
RPD_HPDOUTSEL Internal Pull-down resistance on HPDOUT_SEL 125 250 350 kΩ
CI2C-PINS Capacitance for SCL/CFG0 and SDA/CFG1 f = 100 kHz; 5 pF
C(I2C_FM+_BUS) I2C bus capacitance for FM+ (1 MHz) 150 pF
C(I2C_FM_BUS) I2C bus capacitance for FM (400 kHz) 150 pF
R(EXT_I2C_FM+) External resistors on both SDA and SCL when operating at FM+ (1 MHz) C(I2C_FM+_BUS) = 150 pF 620 820 910 Ω
R(EXT_I2C_FM) External resistors on both SDA and SCL when operating at FM (400 kHz) C(I2C_FM_BUS) = 150 pF 620 1500 2200 Ω
LV_DDC_SDA and LV_DDC_SCL (DDC Buffer Disabled)
VIL_1p2V Low-level input voltage VCC = 3.0 V; -0.3 0.378 V
VIH_1p2V High-level input voltage VCC = 3.6 V; 0.8 3.6 V
VIL_1p8V Low-level input voltage VCC = 3.0 V; -0.3 0.57 V
VIH_1p8V High-level input voltage VCC = 3.6 V; 1.19 3.6 V
VIL_3p3V Low-level input voltage VCC = 3.0 V; -0.3 0.8 V
VIH_3p3V High-level input voltage VCC = 3.6 V; 2.2 3.6 V
DDC Buffer (LV_DDC_SCL, LV_DDC_SDA, HV_DDC_SCL, HV_DDC_SDA)
VHV_IH High-level input voltage for HV_DDC_SCL and HV_DDC_SDA VIO = 3.3 V; VCC = 3.0 V 3.3 5.3 V
VHV_IL Low-level input voltage for HV_DDC_SCL and HV_DDC_SDA VIO = 3.3 V; VCC = 3.0 V -0.3 1.6 V
VLV_IH High-level input voltage for LV_DDC_SCL and LV_DDC_SDA for 1.2-V LVCMOS VIO = 1.14 V; VCC = 3.3 V 0.8 3.6 V
VLV_IH High-level input voltage for LV_DDC_SCL and LV_DDC_SDA for 1.8-V LVCMOS VIO = 1.7 V; VCC = 3.3 V 1.15 3.6 V
VLV_IH High-level input voltage for LV_DDC_SCL and LV_DDC_SDA for 3.3-V LVCMOS VIO = 3.0 V; VCC = 3.3 V 2.1 3.6 V
VLV_IL Low-level input voltage for LV_DDC_SCL and LV_DDC_SDA for 1.2-V LVCMOS VIO = 1.26 V; VCC = 3.3 V -0.3 0.082 * VIO V
VLV_IL Low-level input voltage for LV_DDC_SCL and LV_DDC_SDA for 1.8-V LVCMOS VIO = 1.9 V; VCC = 3.3 V -0.3 0.10 * VIO V
VLV_IL Low-level input voltage for LV_DDC_SCL and LV_DDC_SDA for 3.3-V LVCMOS VIO = 3.6 V; VCC = 3.3 V -0.3 0.10 * VIO V
IHV_IL_FS Failsafe Input leakage for HV_DDC_SCL and HV_DDC_SDA VIN = 5.3 V through 1.5 kΩ; VCC = 0 V; VIO = 0 V; -5 5 µA
IHV_IL Input leakage for HV_DDC_SCL and HV_DDC_SDA HV VIN = 5.3 V; LV VIN = VIO; -5 5 µA
ILV_IL Input leakage for LV_DDC_SCL and LV_DDC_SDA HV VIN = 5.3 V; LV VIN = VIO; -5.5 5.5 µA
IHV_OL Low-level output current VHV_OL = 0.4 V; HDMI5V= 5.3 V; Pullup with 1.4 kΩ; VCC = 3.0 V; 3.5 mA
VHV_OL Low-level output voltage for HV_DDC_SCL and HV_DDC_SDA HDMI5V= 5.3 V; Pullup with 1.4 kΩ; VCC = 3.0 V; 0.4 V
VLV_OL Low-level output voltage for LV_DDC_SCL and LV_DDC_SDA for 1.2-V LVCMOS VCC = 3.0 V; VIO = 1.26 V 0.2 0.3 V
VLV_OL Low-level output voltage for LV_DDC_SCL and LV_DDC_SDA for 1.8-V LVCMOS VCC = 3.0 V; VIO = 1.9 V 0.3 0.4 V
VLV_OL Low-level output voltage for LV_DDC_SCL and LV_DDC_SDA for 3.3-V LVCMOS VCC = 3.0 V; VIO = 3.6 V 0.6 0.75 V
ΔVLV_HYST_3p3V Hysteresis on LV side for 3.3 V LVCMOS VIO = 3.3 V; VCC = 3.3 V 50 mV
RPULV Internal pull-up resistor to VIO 7450 10000 13000 Ω
RPUHV External pull-up resistor to HDMI 5 V 1500 1800 2000 Ω
CIOHV Capacitance for HV_DDC_SCL and HV_DDC_SDA 12 pF
CIOLV Capacitance for LV_DDC_SCL and LV_DDC_SDA 7 pF
VHDMI5V HDMI 5V 4.8 5.3 V
CHV_BUS Bus capacitance for HV_DDC_SCL and HV_DDC_SDA 750 pF
CLV_BUS Bus capacitance for LV_DDC_SCL and LV_DDC_SDA 50 pF
HPD_IN
VIL-HPDIN Low-level input voltage for HPD_IN VCC = 3.6 V; -0.3 0.8 V
VIH-HPDIN High-level input voltage for HPD_IN VCC = 3.6 V 2.0 5.5 V
IH-HPDIN High-level input current for HPD_IN Device powered; VIH = 5.5 V; Includes internal pull-down resistor -50 50 µA
IL-HPDIN Low-level input current for HPD_IN Device powered; VIL = 0 V; Includes internal pull-down resistor -1 1 µA
RPD-HPDIN Internal Pull-down resistance on HPD_IN VCC = 3.3 V; HPD_IN = 5.5 V 110 150 210 kΩ
ILEAK-HPDIN Fail-safe condition leakage current for HPD_IN VCC = 0 V; HPD_IN = 5.5 V -50 50 µA
HPD_OUT
VOH_3p3V High level output voltage when configured for 3.3 V LVCMOS push/pull. VCC = 3.0 V; 2.4 3.465 V
VOH_1p8V High level output voltage when configured for 1.8 V LVCMOS push/pull. VCC = 3.0 V; 1.3 1.95 V
VOL_PP Low level output voltage when configured for push/pull. VCC = 3.0 V; -0.3 0.4 V
VOL_OD Low level output voltage when configured for open drain. VCC = 3.0 V; 0.5 kΩ to 3.6 V load; -0.3 0.4 V
IOH_3p3V High level output current for 3.3-V LVCMOS HPD_IN = VIH-HPDIN; -4 mA
IOL_3p3V Low level output current for 3.3-V LVCMOS HPD_IN = VIL-HPDIN; I2C mode;  4 mA
IOH_1p8V High level output current for 1.8-V LVCMOS HPD_IN = VIH-HPDIN; -1.1 mA
IOL_1p8V Low level output current for 1.8-V LVCMOS HPD_IN = VIL-HPDIN; I2C mode;  1.2 mA
4-LEVEL CONTROL (MODE, LINEAR_EN, EQ1, ADDR/EQ0, TXSLEW, TXPRE, TXSWG)
VTH Threshold "0" / "R" VCC = 3.3 V   0.55   V
VTH Threshold "R" / "F" VCC = 3.3 V   1.65   V
VTH Threshold "F" / "1" VCC = 3.3 V   2.7   V
IIH High-level input current VIH = 3.6 V; VCC = 3.6 V; 20 60 µA
IIL Low-level input current VIL = 0 V; VCC = 3.6 V; –100   -40 µA
R4PU Internal pullup resistance 48 kΩ
R4PD Internal pull-down resistance     98 kΩ
HDMI HIGH SPEED INPUTS
DR_RX_DATA Data lanes data rate 0.25 12 Gbps
DR_RX_CLK Clock lane data rate 0.25 12 Gbps
VID(DC) DC differential input swing At pins; LINEAR_EN = L; 400 1200 mVpp
VID(EYE) Differential input swing eye opening At pins; 75 mVpp
VRX_ASSERT Signal detect assert level. PRBS7 pattern; 12 Gbps; 180 mVpp
VRX_DEASSERT Signal detect deassert level. PRBS7 pattern; 12 Gbps; 110 mVpp
VICM-DC Input DC common mode voltage bias At pins; 2.5 3.3 VCC V
EEQ_12Gbs_MAX_LT Maximum Fixed EQ gain (AC - DC) At 6 GHz; 12 Gbps CTLE; EQ15; DC Gain = 0 dB; Limited Mode; At output of RX; 12 dB
EEQ_12Gbps_MIN_LT Minimum Fixed EQ gain (AC - DC) At 6 GHz; 12 Gbps CTLE; EQ0; DC Gain = 0 dB; Limited Mode; At output of RX; 1.0 dB
EEQ_12Gbps_BYPASS_LT Maximum Fixed EQ Gain when EQ is bypassed. (AC - DC) At 6 GHz; 12 Gbps CTLE; DC Gain = 0 dB; Limited Mode; At output of RX; -1.5 dB
EEQ_6Gbs_MAX_LT Maximum Fixed EQ gain (AC - DC) At 3 GHz; 6 Gbps CTLE; EQ15; DC Gain = 0 dB; Limited Mode; At output of RX; 12.0 dB
EEQ_6Gbps_MIN_LT Minimum Fixed EQ gain (AC - DC) At 3 GHz; 6 Gbps CTLE; EQ0; DC Gain = 0 dB; Limited Mode; At output of RX; 0.6 dB
EEQ_3Gbs_MAX_LT Maximum Fixed EQ gain (AC - DC) At 1.5 GHz; 3 Gbps CTLE; EQ15; DC Gain = 0 dB; Limited Mode; At output of RX; 12 dB
EEQ_3Gbps_MIN_LT Minimum Fixed EQ gain (AC - DC) At 1.5 GHz; 3 Gbps CTLE; EQ0; DC Gain = 0 dB; Limited Mode; At output of RX; 0.8 dB
RINT Input differential impedance when termination is enabled At TTP2; HPD_IN = H;  0℃ ≤ TA ≤ 70℃ 90 100 110 Ω
RINT Input differential impedance when termination is enabled At TTP2; HPD_IN = H; –20℃ ≤ TA ≤ 85℃ 85 100 115 Ω
HDMI HIGH SPEED OUTPUTS (Limited Mode)
VOL_open Single-ended low-level output voltage for DR ≤ 1.65 Gbps data rate DR = 270 Mbps; HPD_IN = H; AC_EN = L (DC-coupled); TXSWG = "F" (1000 mV); TXPRE = "F" (0dB); TX termination open; VCC_EXT = 3.3 V; 25℃  ≤ TA ≤ 85℃; 2.7 2.9 V
VOL_300 Single-ended low-level output voltage 1.65 Gbps < DR ≤ 3.4 Gbps. DR = 3.4 Gbps; HPD_IN = H; AC_EN = L (DC-coupled); TXSWG = "F" (1000 mV); TXPRE = "F" (0 dB); TX termination 300-ohms; VCC_EXT = 3.3 V; 25℃  ≤ TA ≤ 85℃; 2.6 2.9 V
VOL_DAT20 Data lane single-ended low-level output voltage 3.4 Gbps < DR ≤ 6 Gbps. DR = 5.94 Gbps; HPD_IN = H; AC_EN = L (DC-coupled); TXSWG = "F" (1000 mV); TXPRE = "F" (0 dB); VCC_EXT = 3.3 V; 25℃  ≤ TA ≤ 85℃; 2.3 2.9 V
VSWING_DA_14 Single-ended output voltage swing on data lanes with TX term set to open. DR = 1.5 Gbps; HPD_IN = H; AC_EN = L (DC-coupled); TXSWG = "F" (1000 mV); TXPRE = "F" (0 dB); VCC_EXT = 3.3 V; 25℃  ≤ TA ≤ 85℃; 400 500 600 mV
VSWING_DA_14 Single-ended output voltage swing on data lanes with TX term set to 300-ohms. DR = 3.4 Gbps;HPD_IN = H; AC_EN = L (DC-coupled); TXSWG = "F" (1000 mV); TXPRE = "F" (0 dB); VCC_EXT = 3.3 V; 25℃  ≤ TA ≤ 85℃; 400 500 600 mV
VSWING_DA_20 Single-ended output voltage swing on data lanes for HDMI2.0 operation. DR = 5.94 Gbps;HPD_IN = H; AC_EN = L (DC-coupled); TXSWG = "F" (1000 mV); TXPRE = "F" (0 dB); VCC_EXT = 3.3 V; 25℃  ≤ TA ≤ 85℃; 400 500 600 mV
VSWING_CLK_14_OPEN Single-ended output voltage swing on clock lane for DR ≤ 3.4 Gbps datarate HPD_IN = H; AC_EN = L (DC-coupled); TXSWG = "F" (1000 mV); TXPRE = "F" (0 dB); VCC_EXT = 3.3 V; 25℃  ≤ TA ≤ 85℃; TERM set to open; 400 500 600 mV
VSWING_CLK_20 Single-ended output voltage swing on clock lane for HDMI 2.0 HPD_IN = H; AC_EN = L (DC-coupled); TXSWG = "F" (1000 mV); TXPRE = "F" (0 dB); VCC_EXT = 3.3 V; 25℃  ≤ TA ≤ 85℃;  300 400 600 mV
VOCM-DC-ON FRL DC common mode voltage when actively transmitting At TTP4; AC_EN = L or H; LTP5, 6, 7 or 8; TXFFE0; 25℃  ≤ TA ≤ 85℃; 2.335 3.495 V
VOCM-DC-OFF FRL DC common mode voltage when lane 3 is disabled At TTP4; FRL 3 lane mode; AC_EN = L or H; 25℃  ≤ TA ≤ 85℃; 2.335 3.495 V
VOD_3G Data lanes Differential output swing At TTP4; 2.97 Gbps; HPD_IN = H; AC_EN = L or H; TXSWG = "F" (1000 mV); TXPRE = "F" (0 dB); 25℃  ≤ TA ≤ 85℃; 400 1560 mV
VOD_6G Data lanes Differential output swing At TTP4_EQ; 5.94 Gbps; HPD_IN = H; AC_EN = L or H; TXSWG = "F" (1000 mV); TXPRE = "F" (0 dB); 25℃  ≤ TA ≤ 85℃; 150 1560 mV
VOD_12G_FRL Data lanes Differential output swing at 12 G FRL. At TTP4_EQ; 12 Gbps;  HPD_IN = H; AC_EN = L or H; TXSWG = "F" (1000 mV); TXFFE0; 25℃  ≤ TA ≤ 85℃; 100 1560 mV
ILEAK Failsafe condition leakage current VCC = 0 V; DC-coupled; TMDS output pulled to 3.465 V with 50 Ω resistors 35 µA
IOS Short circuit current limit OUT_CLK, OUT_D[2:0] outputs P or N shorted to GND 70 mA
RTERM14 Internal termination for DR ≤ 3.4 Gbps when DC-coupled TERM = 1h; AC_EN = L (DC-coupled);HPD_IN=H; Active state; –20℃ ≤ TA ≤ 85℃;  235 295 375 Ω
RTERM14 Internal termination for DR ≤ 3.4 Gbps when AC-coupled TERM = 1h; AC_EN = H (AC-coupled); HPD_IN=H; Active state; –20℃ ≤ TA ≤ 85℃;  235 295 375 Ω
RTERM2+ Internal termination for DR > 3.4 Gbps when DC-coupled. TERM = 3h; AC_EN = L (DC-coupled); HPD_IN=H; Active state; –20℃ ≤ TA ≤ 85℃;  85 100 115 Ω
RTERM2+ Internal termination for DR > 3.4 Gbps when AC-coupled. TERM = 3h; AC_EN = H (AC-coupled); HPD_IN=H; Active state; –20℃ ≤ TA ≤ 85℃;  85 100 115 Ω
VTXPRE0-RATIO Transmitter FFE pre-emphasis ratio for 0 dB. TERM = 3h; HPD_IN = H; TX_AC_EN = 0; CLK_TXFFE = 0h; CLK_VOD = 3h; D0_TXFFE = 0h; D0_VOD = 3h; D1_TXFFE = 0h; D1_VOD = 3h; D2_TXFFE = 0h; D2_VOD = 3h; 20 * log (Vp/Vn); 128 zeros followed by 128 ones; 0 dB
VTXPRE1-RATIO Transmitter FFE pre-emphasis ratio for 3.5 dB for data lanes At 5.94 Gbps HDMI 2.0; TERM = 3h; HPD_IN = H; TX_AC_EN = 0; CLK_TXFFE = 0h; CLK_VOD = 3h; D0_TXFFE = 1h; D0_VOD = 3h; D1_TXFFE = 1h; D1_VOD = 3h; D2_TXFFE = 1h; D2_VOD = 3h; 20 * log (Vp/Vn); 128 zeros followed by 128 ones; 4.0 dB
VTXPRE2-RATIO Transmitter FFE pre-emphasis ratio for 6 dB for data lanes At 5.94 Gbps HDMI 2.0; TERM = 3h; HPD_IN = H; TX_AC_EN = 0; CLK_TXFFE = 0h; CLK_VOD = 3h; D0_TXFFE = 2h; D0_VOD = 3h; D1_TXFFE = 2h; D1_VOD = 3h; D2_TXFFE = 2h; D2_VOD = 3h; 20 * log (Vp/Vn); 128 zeros followed by 128 ones; 6.5 dB
VTXFFE0-RATIO Transmitter FRL TXFFE0 de-emphasis ratio At 12 Gbps FRL; TERM = 3h; HPD_IN = H; TX_AC_EN = 0; CLK_TXFFE = 4h; CLK_VOD = 3h; D0_TXFFE = 4h; D0_VOD = 3h; D1_TXFFE = 4h; D1_VOD = 3h; D2_TXFFE = 4h; D2_VOD = 3h; 20 * log (Vp/Vn); 128 zeros followed by 128 ones; -2.5 dB
VTXFFE1-RATIO Transmitter FRL TXFFE1 de-emphasis ratio At 12 Gbps FRL; TERM = 3h; HPD_IN = H; TX_AC_EN = 0; CLK_TXFFE = 5h; CLK_VOD = 3h; D0_TXFFE = 5h; D0_VOD = 3h; D1_TXFFE = 5h; D1_VOD = 3h; D2_TXFFE = 5h; D2_VOD = 3h; 20 * log (Vp/Vn); 128 zeros followed by 128 ones; -3.2 dB
VTXFFE2-RATIO Transmitter FRL TXFFE2 de-emphasis ratio. At 12 Gbps FRL; TERM = 3h; HPD_IN = H; TX_AC_EN = 0; CLK_TXFFE = 6h; CLK_VOD = 3h; D0_TXFFE = 6h; D0_VOD = 3h; D1_TXFFE = 6h; D1_VOD = 3h; D2_TXFFE = 6h; D2_VOD = 3h; 20 * log (Vp/Vn); 128 zeros followed by 128 ones; -3.5 dB
VTXFFE3-RATIO Transmitter FRL TXFFE3 de-emphasis ratio At 12 Gbps FRL; TERM = 3h; HPD_IN = H; TX_AC_EN = 0; CLK_TXFFE = 7h; CLK_VOD = 3h; D0_TXFFE = 7h; D0_VOD = 3h; D1_TXFFE = 7h; D1_VOD = 3h; D2_TXFFE = 7h; D2_VOD = 3h; 20 * log (Vp/Vn); 128 zeros followed by 128 ones; -4.5 dB
HDMI HIGH SPEED OUTPUTS (Linear Mode)
CPLF-TXSWG-0 Low-frequency 1-dB compression point Dx_VOD = 0. At 10 MHz; 200 mVpp < VID < 1200 mVpp; EQ0; DCGAIN = 0 dB; 12Gbps CTLE; CTLEBYP_EN = 0; BERT TX 100 MHz clock starting at  200 mV to 1200 mV in 50 mV steps;TX DC coupled to VCC_EXT; 900 mVpp
CPHF-TXSWG-0 High-frequency 1-dB compression point Dx_VOD = 0. At 6 GHz; 200 mVpp < VID < 1200 mVpp; EQ0; DCGAIN = 0 dB; 12 Gbps CTLE;  CTLEBYP_EN = 0; TX DC coupled to VCC_EXT; 750 mVpp
CPLF-TXSWG-R Low-frequency 1-dB compression point Dx_VOD = 1. At 10 MHz; 200 mVpp < VID < 1200 mVpp; EQ0; DCGAIN = 0 dB; 12 Gbps CTLE; CTLEBYP_EN = 0; BERT TX 100 MHz clock starting at  200 mV to 1200 mV in 50 mV steps; TX DC coupled to VCC_EXT; 1000 mVpp
CPHF-TXSWG-R High-frequency 1-dB compression point Dx_VOD = 1. At 6 GHz; 200 mVpp < VID < 1200 mVpp; EQ0; DCGAIN = 0 dB; 12Gbps CTLE; CTLEBYP_EN = 0;TX DC coupled to VCC_EXT; 800 mVpp
CPLF-TXSWG-F Low-frequency 1-dB compression point Dx_VOD = 2. At 10 MHz; 200 mVpp < VID < 1200 mVpp; EQ0; DCGAIN = 0 dB; 12 Gbps CTLE; CTLEBYP_EN = 0; BERT TX 100 MHz clock starting at  200 mV to 1200 mV in 50 mV steps; TX DC coupled to VCC_EXT; 1100 mVpp
CPHF-TXSWG-F High-frequency 1-dB compression point Dx_VOD = 2. At 6 GHz; 200 mVpp < VID < 1200 mVpp; EQ0; DCGAIN = 0 dB; 12 Gbps CTLE; CTLEBYP_EN = 0; TX DC coupled to VCC_EXT; 875 mVpp
CPLF-TXSWG-1 Low-frequency 1-dB compression point Dx_VOD = 3. At 10 MHz; 200 mVpp < VID < 1200 mVpp; EQ0; DCGAIN = 0 dB; 12 Gbps CTLE; CTLEBYP_EN = 0; BERT TX 100 MHz clock starting at  200 mV to 1200 mV in 50 mV steps; TX DC coupled to VCC_EXT; 1200 mVpp
CPHF-TXSWG-1 High-frequency 1-dB compression point Dx_VOD = 3. At 6 GHz; 200 mVpp < VID < 1200 mVpp; EQ0; DCGAIN = 0 dB; 12 Gbps CTLE; CTLEBYP_EN = 0; TX DC coupled to VCC_EXT; 950 mVpp