SLLSG10 November   2024 TDP142-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Power Supply Characteristics
    6. 5.6 Control I/O DC Electrical Characteristics
    7. 5.7 DP Electrical Characteristics
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DisplayPort
      2. 6.3.2 Configuration Jumper Levels
      3. 6.3.3 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO Mode
      2. 6.4.2 Device Configuration in I2C Mode
      3. 6.4.3 Linear EQ Configuration
      4. 6.4.4 Operation Timing – Power Up
    5. 6.5 Programming
  9. 7 Register Maps
    1. 7.1 TDP142-Q1 Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ESD Protection
    2. 8.2 Typical Application
      1. 8.2.1 Source Application Implementation
        1. 8.2.1.1 Design Requirement
        2. 8.2.1.2 Detail Design Procedure
      2. 8.2.2 Sink Application Implementation
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.2 Detailed Design Procedure

The design procedure for sink application is listed as follows:

  • Determine the loss profile on the DP input (C) and output (D) channels and cables. See Figure 8-5 for 6mil trace insertion loss.
  • Based on the loss profile, determine the optimal configuration for the TDP142, to pass electrical compliance.
  • See Figure 8-4 for information on the source application that uses AC coupling capacitors, control pin resistors, and the recommended decouple capacitors from VCC pins to ground.
    • AUX: Make sure the AUXP has a 1MΩ pullup resistor and the AUXN has a 1MΩ pulldown resistor. The 1MΩ resistors must be on the TDP142-Q1 side of the 100nF capacitors.
    • HPDIN: Route the HPD signal to either pin 23 or pin 32 based on the GPIO/I2C mode. With this setup, the TDP142-Q1 is able to conserve power when a source is not connected.
      Table 8-6 HPD GPIO/I2C Selection
      MODE HPD
      GPIO (I2C_EN = 0) Pin 32
      I2C (I2C_EN != 0) Pin 23

  • Configure the TDP142-Q1 using the GPIO terminals or the I2C interface:
    • GPIO – Using the terminals DPEQ0 and DPEQ1.
    • TI recommends to start a higher equalization value like 13dB and 15dB first and adjust the value if necessary.
    • I2C – Refer to the I2C Register Maps and the Programming section for a detail configuration procedures.
  • The thermal pad must be connected to ground.