SNLS745A November   2023  – April 2024 TDP2004

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Linear Equalization
      2. 6.3.2 Flat-Gain
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin mode
        1. 6.5.1.1 Five-Level Control Inputs
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
      3. 6.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 DP 2.1 Mainlink Signal Conditioning
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNQ|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.1 Linear Equalization

The TDP2004 receivers feature a continuous-time linear equalizer (CTLE) that applies high-frequency boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects of the passive channel. The receivers implement two stage linear equalizer for wide range of equalization capability. The equalizer stages also provide flexibility to make subtle modifications of mid-frequency boost for best EQ gain profile match with wide range of channel media characteristics. The EQ profile control feature is only available in SMBus/I2C mode. In Pin mode the settings are optimized for FR4 traces.

Table 6-1 provides available equalization boost at 20Gbps (10GHz Nyquist frequency) through EQ control pins or SMBus/I2C registers. In Pin Control mode EQ1 and EQ0 pins set equalization boost for channels 0-3. In I2C mode individual channels can be independently programmed for EQ boost. If the TDP2004 is used for other data rates equalization gain can be extracted from Figure 5-1.

Table 6-1 Equalization Control Settings
EQUALIZATION SETTING TYPICAL EQ BOOST (dB)
EQ INDEX Pin mode SMBus/I2C Mode at 10GHz
EQ1 EQ0 eq_stage1_3:0 eq_stage2_2:0 eq_profile_3:0 eq_stage1_bypass
0 L0 L0 0 0 0 1 4.0
1 L0 L1 1 0 0 1 5.0
2 L0 L2 3 0 0 1 7.0
5 L1 L0 0 0 1 0 8.0
6 L1 L1 1 0 1 0 9.0
7 L1 L2 2 0 1 0 9.5
8 L1 L3 3 0 3 0 10.0
9 L1 L4 4 0 3 0 11.0
10 L2 L0 5 1 7 0 12.0
11 L2 L1 6 1 7 0 12.5
12 L2 L2 8 1 7 0 13.5
13 L2 L3 10 1 7 0 14.5
14 L2 L4 10 2 15 0 15.0
15 L3 L0 11 3 15 0 15.5
16 L3 L1 12 4 15 0 16.5
17 L3 L2 13 5 15 0 17.0
18 L3 L3 14 6 15 0 18.0
19 L3 L4 15 7 15 0 19.0