SNLS745A November   2023  – April 2024 TDP2004

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Linear Equalization
      2. 6.3.2 Flat-Gain
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin mode
        1. 6.5.1.1 Five-Level Control Inputs
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
      3. 6.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 DP 2.1 Mainlink Signal Conditioning
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNQ|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 DC Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power
PACT Device active power 4 channels active, EQ = 0-2 0.57 0.71 W
4 channels active, EQ = 5-19 0.69 0.85 W
PSTBY Device power consumption in standby power mode All channels disabled (PD = H) 17 25 mW
Control IO
VIH High level input voltage SDA, SCL, PD, READ_EN_N pins 2.1 V
VIL Low level input voltage SDA, SCL, PD, READ_EN_N pins 1.08 V
VOH High level output voltage Rpullup = 4.7kΩ (SDA, SCL, DONEn pins) 2.1 V
VOL Low level output voltage IOL = –4mA (SDA, SCL, DONEn pins) 0.4 V
IIH Input high leakage current VInput = VCC, (SCL, SDA, PD, READ_EN_N pins) 10 µA
IIL Input low leakage current VInput = 0V, (SCL, SDA, PD, READ_EN_N pins) –10 µA
IIH,FS Input high leakage current for fail safe input pins VInput = 3.6V, VCC = 0V, (SCL, SDA, PD, READ_EN_N pins) 200 µA
CIN-CTRL Input capacitance SDA, SCL, PD, READ_EN_N pins 1.6 pF
5 Level IOs (MODE, GAIN, EQ0, EQ1 pins)
IIH_5L Input high leakage current, 5-level IOs VIN = 2.5V 10 µA
IIL_5L Input low leakage current for all 5-level IOs except MODE. VIN = GND –10 µA
IIL_5L,MODE Input low leakage current for MODE pin VIN = GND –200 µA
Receiver
VRX-DC-CM RX DC common vode voltage Device is in active or standby state 1.4 V
ZRX-DC Rx DC single-ended impedance 50 Ω
Transmitter
ZTX-DIFF-DC DC differential Tx impedance Impedance of Tx during active signaling, VID,diff = 1Vpp 100 Ω
VTX-DC-CM Tx DC common mode voltage 1.0 V
ITX-SHORT Tx short circuit current Total current the Tx can supply when shorted to GND 70 mA