SNLS746 June   2024 TDP2044

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Linear Equalization
      2. 6.3.2 Flat-Gain
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin mode
        1. 6.5.1.1 Five-Level Control Inputs
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
      3. 6.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 USB Type-C DP Only Source Applications
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.1.2 Detailed Design Procedure

The TDP2044 provides signal conditioning for four DP mainlink channels along with 4:4 cross-point (channel re-orientation) function. The device is a linear redriver which is agnostic to DP link training. The DP link training negotiation between a display source and sink stays effective through the device. The redriver becomes part of the electrical channel along with passive traces, cables, and other channel elements, resulting in optimum source and sink parameters for best electrical link. Figure 7-2 shows a simplified schematic for DisplayPort application using TDP2044 to implement USB Type-C DP alternate mode in a source application. A USB power delivery (PD) device control the cross-point mux polarity signal SEL according to USB Type-C cable plug position.

TDP2044 Simplified Schematic for USB-C Alternate Mode Source Application Figure 7-2 Simplified Schematic for USB-C Alternate Mode Source Application
Note:

DisplayPort side-band signals AUXp,n and HPD are bypassed. An external mux such as TMUXHS221 can provide flipping functions for SBU signals as illustrated in Figure 7-2. An inverted HPD signal can be used to control the device standby operation using the PD pin; however appropriate filtering out of HPD interrupt signals must be provisioned.

In some applications where a microcontroller or other link monitoring device has DP link state information, the controller can exercise I2C registers of TDP2044 for additional power management.

Table 7-1 shows how DP signals are routed to a USB Type-C connector for a source applications for both SEL = 0 and SEL =1 configurations

Table 7-1 DP Alt Mode Source Pin Assignment C or E
SEL pin DP Lane from Source TDP2044 RX PIN TDP2044 TX PIN USB-C Receptacle pin
0 DP0P/N RX0P/N TX0P/N RXP/N2
0 DP3P/N RX1P/N TX1P/N RXP/N1
0 DP1P/N RX2P/N TX2P/N TXP/N2
0 DP2P/N RX3P/N TX3P/N TXP/N1
1 DP0P/N RX0P/N TX1P/N RXP/N1
1 DP3P/N RX1P/N TX0P/N RXP/N2
1 DP1P/N RX2P/N TX3P/N TXP/N1
1 DP2P/N RX3P/N TX2P/N TXP/N2

While a DP alternate mode sink implementation is similar, the TDP2044 can not support both configuration C and E in the same DP sink board. If the both configurations are required the DP Sink must handle the DP lane order and polarity inversion. Most sink implementations use configuration C illustrated inTable 7-2.

Table 7-2 DP Alt Mode Sink Pin Assignment C
SEL pin USB-C Receptacle pin TDP2044 RX PIN TDP2044 TX PIN DP Lane to Sink
0 TXP/N2 RX0P/N TX0P/N DP0P/N
0 TXP/N1 RX1P/N TX1P/N DP3P/N
0 RXP/N2 RX2P/N TX2P/N DP1P/N
0 RXP/N1 RX3P/N TX3P/N DP2P/N
1 TXP/N1 RX0P/N TX1P/N DP0P/N
1 TXP/N2 RX1P/N TX0P/N DP3P/N
1 RXP/N1 RX2P/N TX3P/N DP1P/N
1 RXP/N2 RX3P/N TX2P/N DP2P/N

USB PD controller is used to negotiate DP Alternate Mode with a link partner. USB PD specification require that the TDP2044 TX/RX pins connected to USB Type-C pins support USB safe state electrical requirements. To support USB safe state the TDP2044 must be entered into standby mode with PD = H. Table 7-3 shows electrical characteristics in standby mode.

Table 7-3 TX and RX Pins in Standby Mode
Parameters Standby mode (PD = H)
Rx CMV 1.4V
Rx impedance to GND 230K
Tx CMV 0.9V
Tx impedance to GND 3M