SNLS766 July   2024 TDP20MB421

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High-Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 5-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 Flat Gain
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 DP 2.1 Mainlink Signal Conditioning
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5.2 SMBUS/I2C Register Control Interface

If MODE = L2 (SMBus / I2C secondary control mode), the TDP20MB421 is configured for best signal integrity through a standard I2C or SMBus interface operates up to 400kHz. Pin strap settings determines the secondary address of the TDP20MB421 on the ADDR and MODE pins. Table 6-4 provides the eight possible secondary addresses (7-bit) for each channel banks of the device. In SMBus and I2C modes, the SCL and SDA pins connect to a 3.3V supply through a pullup resistor. The value of the resistor depends on the total bus capacitance. 4.7kΩ is a good first approximation for a bus capacitance of 10pF.

Table 6-4 SMBUS/I2C Secondary Address Settings
MODEADDR7-bit Secondary Address Channels 2-37-bit Secondary Address Channels 0-1
L1L00x180x19
L1L10x1A0x1B
L1L20x1C0x1D
L1L30x1E0x1F
XL4ReservedReserved
L2L00x200x21
L2L10x220x23
L2L20x240x25
L2L30x260x27

The TDP20MB421 has two types of registers:

  • Shared Registers: These registers are accessible at any time and are used for device-level configuration, status read back, control, and to read the device ID information.
  • Channel Registers: These registers control and configure specific features for each channel. All channels have the same register set and can be configured independently or as a group through broadcast writes to Bank 0 or 1.

The TDP20MB421 features two banks of channels, Bank 0 (Channels 2-3) and Bank 1 (Channels 0-1), each feature a separate register set and require a unique SMBus secondary address.

Channel Registers Base AddressChannel Bank 0 AccessChannel Bank 1 Access
0x00Channel 3 registersChannel 1 registers
0x20Channel 3 registersChannel 1 registers
0x40Channel 2 registersChannel 0 registers
0x60Channel 2 registersChannel 0 registers
0x80

Broadcast write channel Bank 0 registers,

read channel 3 registers

Broadcast write channel Bank 1 registers,

read channel 1 registers

0xE0Bank 0 Share registersBank 1 Share registers