SNLS766 July   2024 TDP20MB421

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High-Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 5-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 Flat Gain
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 DP 2.1 Mainlink Signal Conditioning
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.2 Linear Equalization

The TDP20MB421 receivers feature a continuous time linear equalizer (CTLE) that applies high-frequency boost and low-frequency attenuation to equalize the frequency-dependent insertion loss effects of a passive channel. The receivers implement a 2-stage linear equalizer for a wide range of equalization capability. The equalizer stages also provide flexibility to make subtle modifications to the mid-frequency boost for the best EQ-gain profile match with a wide range of channel media characteristics. The control feature of the EQ profile is only available in SMBus/I2C Mode. In Pin Mode, the settings are optimized for FR4 traces.

Table 6-2 shows available equalization boost through EQ control pins or SMBus/I2C registers. In Pin Control mode, EQ1 and EQ0 pins set the equalization boost for all channels. In I2C Mode, individual channels can be independently programmed for an EQ boost.

Table 6-2 Equalization Control Settings
EQUALIZATION SETTINGTYPICAL EQ BOOST (dB)
EQ INDEXPin modeSMBus/I2C Modeat 10 GHz
EQ1EQ0eq_stage1_3:0eq_stage2_2:0eq_profile_3:0eq_stage1_bypass
0L0L000014.0
1L0L110015.0
2L0L230017.0
5L1L000108.0
6L1L110109.0
7L1L220109.5
8L1L3303010.0
9L1L4403011.0
10L2L0517012.0
11L2L1617012.5
12L2L2817013.5
13L2L31017014.5
14L2L410215015.0
15L3L011315015.5
16L3L112415016.5
17L3L213515017.0
18L3L314615018.0
19L3L415715019.0