SLDS190B November   2012  – March 2022 TFP401A-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Digital I/O Electrical Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 TMDS Pixel Data and Control Signal Encoding
      2. 7.3.2 TFP401A-Q1 Clocking and Data Synchronization
      3. 7.3.3 TFP401A-Q1 TMDS Input Levels and Input Impedance Matching
      4. 7.3.4 TFP401A-Q1 Device Incorporates HSYNC Jitter Immunity
    4. 7.4 Device Functional Modes
      1. 7.4.1 TFP401A-Q1 Modes of Operation
      2. 7.4.2 TFP401A-Q1 Output Driver Configurations
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Design Requirements
        2. 8.1.1.2 Detailed Design Procedure
          1. 8.1.1.2.1 Data and Control Signals
          2. 8.1.1.2.2 Configuration Options
          3. 8.1.1.2.3 Power Supplies Decoupling
        3. 8.1.1.3 Application Curves
        4. 8.1.1.4 DVDD
        5. 8.1.1.5 OVDD
        6. 8.1.1.6 AVDD
        7. 8.1.1.7 PVDD
    2. 8.2 Power Supply Recommendations
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
        1. 8.3.1.1 Layer Stack
        2. 8.3.1.2 Routing High-Speed Differential Signal Traces (RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+)
      2. 8.3.2 Layout Example
      3. 8.3.3 TI PowerPAD 100-TQFP Package
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 TMDS Pixel Data and Control Signal Encoding

The device transmits only one of two possible transition-minimized differential signaling (TMDS) characters for a given pixel at a given time. The transmitter keeps a running count of the number of ones and zeros previously sent, and transmits the character that minimizes the number of transitions to approximate a dc balance of the transmission line.

Reception of RGB pixel data during active display time uses three TMDS channels, DE = high. The same three channels also receive control signals, HSYNC, VSYNC, and user-defined control signals CTL[3:1]. Reception of these control signals occurs during inactive display or blanking-time. Blanking-time is when DE = low. The following table maps the received input data to the appropriate TMDS input channel in a DVI-compliant system.

Table 7-1 TMDS Pixel Data and Control Signal Encoding
RECEIVED PIXEL DATA
ACTIVE DISPLAY DE = HIGH		INPUT CHANNELOUTPUT PINS
(VALID FOR DE = HIGH)
Red[7:0]Channel-2 (Rx2 ±)QE[23:16] QO[23:16]
Green[7:0]Channel-1 (Rx1 ±)QE[15:8] QO[15:8]
Blue[7:0]Channel-0 (Rx0 ±)QE[7:0] QO[7:0]
RECEIVED CONTROL DATA
BLANKING DE = LOW		INPUT CHANNELOUTPUT PINS
(VALID FOR DE = LOW)
CTL[3:2]Channel-2 (Rx2 ±)CTL[3:2]
CTL[1: 0](1)Channel-1 (Rx1 ±)CTL1
HSYNC, VSYNCChannel-0 (Rx0 ±)HSYNC, VSYNC
(1) Some TMDS transmitters transmit a CTL0 signal. The TFP401A-Q1 device decodes and transfers CTL[3:1] and ignores CTL0 characters. CTL0 is not available as a TFP401A-Q1 output.

The TFP401A-Q1 device discriminates between valid pixel TMDS characters and control TMDS characters to determine the state of active display versus blanking, in effect, the state of DE.