SLOS423K september   2003  – april 2023 THS3091 , THS3095

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = ±15 V
    6. 7.6 Electrical Characteristics: VS = ±5 V
    7. 7.7 Typical Characteristics: ±15 V
    8. 7.8 Typical Characteristics: ±5 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-Down and Reference Pins Functionality
    4. 8.4 Device Functional Modes
      1. 8.4.1 Wideband, Noninverting Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 PowerPAD Design Considerations
          1. 9.4.1.1.1 PowerPAD Layout Considerations
        2. 9.4.1.2 Power Dissipation and Thermal Considerations
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 Power-Down and Reference Pins Functionality

The THS3095 features a power-down pin (PD) designed to reduce system power that lowers the quiescent current from 9.5 mA down to 500 μA. The THS3095 also features a reference pin (REF) that allows the user to control the enable or disable power-down voltage levels applied to the PD pin.

The power-down pin of the amplifier defaults to the positive supply voltage in the absence of an applied voltage, putting the amplifier in the power-on mode of operation. Driving the power-down pin towards the negative rail will turn off the amplifier and conserve power The following equations show the relationship between the reference voltage and the power-down thresholds:

Equation 1. PD ≤   R E F   +   0.8   V   f o r   d i s a b l e
Equation 2. PD ≤   R E F   +   2.0   V   f o r   e n a b l e

where the usable range at the REF pin is:

Equation 3.   V S -   ≤   V R E F   ≤   V S + -   4   V

The recommended mode of operation is to tie the REF pin to midrail, thus setting the disable or enable thresholds to the following equations:

Equation 4.   V m i d r a i l   +   0 . 8   V
Equation 5.   V m i d r a i l   +   2   V

Power-Down mode is not intended to provide a high-impedance output. In other words, the power-down functionality is not intended to allow use as a tri-state bus driver. When in Power-Down mode, the impedance at the output of the amplifier is dominated by the feedback and gain-setting resistors, but the output impedance of the device varies depending on the voltage applied to the outputs.

Figure 8-1 shows the total system output impedance, which includes the amplifier output impedance in parallel with the feedback plus gain resistors, and cumulates to 2416 Ω. Figure 8-2 shows this circuit configuration for reference.

GUID-20230213-SS0I-FKGZ-5F0D-L8L47DNRGBPP-low.svg Figure 8-1 Power-Down Output Impedance vs Frequency

As with most current feedback amplifiers, the internal architecture places some limitations on the system when in Power-Down mode. Most notably is the fact that the amplifier actually turns on if there is a ±0.7 V or greater difference between the two input nodes (VIN+ and VIN-) of the amplifier. If this difference exceeds ±0.7 V, then the output of the amplifier creates an output voltage equal to approximately [(VIN+ – VIN–) – 0.7 V] × Gain. This also implies that if a voltage is applied to the output while in Power-Down mode, the V– node voltage is equal to VO(applied) × RG / (RF + RG). For low-gain configurations and a large applied voltage at the output, the amplifier can actually turn on due to the aforementioned behavior.

The time delays associated with turning the device on and off are specified as the time required for the amplifier to reach either 10% or 90% of the final output voltage. The time delays are in the order of microseconds because the amplifier moves in and out of the linear mode of operation in these transitions.