To optimize performance with a high-frequency amplifier, such as the THS309x, pay careful attention to board layout parasitic and external component types.

Recommendations to optimize performance include the following:

• Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and input pins can cause instability. To reduce unwanted capacitance, open a window around the signal I/O pins in all of the ground and power planes around those pins. Otherwise, keep ground and power planes unbroken elsewhere on the board.
• Minimize the distance [< 0.25 inch (6.35 mm)] from the power supply pins to the high-frequency 0.1‑μF and 100‑pF decoupling capacitors. At the device pins, keep the ground and power plane layout away from the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. Always decouple the power-supply connections with these capacitors. Use larger (6.8 μF or more) tantalum decoupling capacitors, effective at lower frequency, on the main supply pins. The decoupling capacitors can be placed somewhat farther from the device, and can be shared among several devices in the same area of the printed circuit board (PCB).
• Connections to other wideband devices on the board can be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Use relatively wide traces [0.05 inch (1.3 mm) to 0.1 inch (2.54 mm)], preferably with ground and power planes opened up around the traces. Estimate the total capacitive load and determine if isolation resistors on the outputs are necessary. Low-parasitic capacitive loads (< 4 pF) may not need an R_ISO because the THS309x are nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an R_ISO are allowed as the signal gain increases (increasing the unloaded phase margin).