The most basic operation is to ground VREF (pin 14), and use the internal connection from the D2S to the OPS to provide a differential to single-ended, high-power driver. Figure 8-15 shows the characterization circuit used for the combined performance specifications.

Figure 8-15 Differential to Single-Ended, Gain of 5 V/V Configuration

This configuration shows the test circuit used to generate Figure 6-1. Some of the key features in this basic configuration include:

1. The power supplies are brought into the OPS first, then back to the input stage through a π-filter comprised of a ferrite bead and local decoupling capacitors on –VCC2 and +VCC2 (pins 5 and 16, respectively). See the Section 10 section for more information.
2. The two logic lines are grounded. This logic configuration (with pin 7 grounded) selects the internal path from the D2S to OPS, and enables the OPS.
3. The external I/O pins of the midscale buffer are left floating.
4. The VREF pin is grounded, thus setting the D2S output common-mode voltage at VO1 (pin 6) to ground.
5. The D2S external output is loaded with a 200 Ω resistor to ground. Lighter loading on the VO1 pin (versus the 100 Ω used to characterize the D2S only) results in increased frequency response peaking. Heavier loading degrades the D2S distortion performance.
6. The external OPS input at VIN+ (pin 9) is left floating. However, VIN+ is internally tied to ground by the internal 18.5 kΩ resistor.
7. The feedback resistor in the OPS is set to the parallel combination of the external 249 Ω resistor and the internal 18.5 kΩ resistor. This 245.7 Ω total R_F with the 162 Ω R_G resistor results in a gain of approximately 2.5 V/V (7.98 dB) in the OPS.
8. The input D2S provides a gain of 2 V/V (6 dB), and along with the 2.5 V/V (7.98 dB) from the OPS, results in an overall gain of 5 V/V (13.98 dB) with > 600 MHz of SSBW (see Figure 6-1).