The OPS provides modest dc precision with typical, minimum, and maximum dc error terms in Table 8-4. The input offset voltage applies to either input path with very little difference between the internal and external paths.

Selecting the internal path results in no source resistance for I_bn, so that term drops out. When the external path is selected, a dc source impedance may be present, so the I_bn term creates another error term, and adds to the total output offset.

Stepping through an example design for the OPS output dc offset using the external path with a low insertion loss filter shown in Figure 8-17, along with its R_F and R_G values, gives the following results:

• R_S for the I_bn term = 90.9 Ω || 464 Ω = 76 Ω. (dc source impedance for the filter design)
• R_F including the internal 18.5 kΩ resistor = 205 Ω || 18.5 kΩ = 202.7 Ω
• Resulting gain with the 102 Ω R_G element = 2.99 V/V

Table 8-5 shows the typical and worst-case output error terms. Note that a positive current out of the noninverting input gives a positive output offset term, whereas a positive current out of the inverting input gives a negative output term.

The input offset voltage dominates the error terms. The worst-case numbers are calculated by adding the individual errors algebraically, but is rarely seen in practice. None of the OPS input dc error terms are correlated. To compute output drift numbers, use the same gains shown in Table 8-5 with the specified drift numbers.

The OPS PATHSEL control responds extremely quickly with low-switching glitches, as shown in Figure 8-11. For this test, the D2S input is set to GND, and the output of the D2S is connected to the external OPS input. The PATHSEL switch is then toggled at 10 MHz. The results show the offset between the internal and external paths as well matched.

Figure 8-11 OPS Path-Select Switching Glitch

The OPS includes a disable feature that reduces power consumption from approximately 11 mA to 2 mA. The logic controls are intended to be ground-referenced regardless of the power supplies used. The logic reference (GND, pin 7) is normally grounded and also provides a connection to the internal 18.5 kΩ resistor on VIN+ (pin 9, default bias to pin 7). Operating in a single-supply configuration with –V_CC at GND and the external OPS input (VIN+) floated, places VIN+ internally at –V_CC = GND. Driving the external OPS input (VIN+) from a source within the operating range overrides the bias to –V_CC. However, if the application requires VIN+ to be floated in a single-supply operation, consider centering the voltage on VIN+ with an added 18.5 kΩ external resistor to the +V_CC supply.

If the disable feature is not needed, simply float or ground DISABLE (pin 10) to hold the OPS in the enabled state. Increasing the voltage on the DISABLE pin to greater than 1.3 V disables the OPS and reduces the current to approximately 2 mA. In a single-supply design, the OPS can be disabled by setting DISABLE to +V_CC, even up to the maximum operating supply of 15.8 V.

Do not move the logic threshold away from those set by the logic ground at pin 7. If a different logic swing level is required, and GND (pin 7) is biased to a different voltage, be sure the source can sink the typical 280 µA coming out of GND. Also recognize that the 18.5 kΩ bias resistor on the external OPS input (VIN+) is connected to GND voltage internally.

As shown in Figure 6-56, the OPS enables in approximately 100 ns from the logic threshold at 1.0 V, while disabling to a final value in approximately 500 ns.