SBOS780C March   2016  – June 2021 THS3215

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: D2S
    6. 6.6  Electrical Characteristics: OPS
    7. 6.7  Electrical Characteristics: D2S + OPS
    8. 6.8  Electrical Characteristics: Midscale (DC) Reference Buffer
    9. 6.9  Typical Characteristics: D2S + OPS
    10. 6.10 Typical Characteristics: D2S Only
    11. 6.11 Typical Characteristics: OPS Only
    12. 6.12 Typical Characteristics: Midscale (DC) Reference Buffer
    13. 6.13 Typical Characteristics: Switching Performance
    14. 6.14 Typical Characteristics: Gain Drift
  7. 7 Parameter Measurement Information
    1. 7.1 Overview
    2. 7.2 Frequency Response Measurement
    3. 7.3 Harmonic Distortion Measurement
    4. 7.4 Noise Measurement
    5. 7.5 Output Impedance Measurement
    6. 7.6 Step-Response Measurement
    7. 7.7 Feedthrough Measurement
    8. 7.8 Midscale Buffer ROUT Versus CLOAD Measurement
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Differential to Single-Ended Stage (D2S) With Fixed Gain of 2 V/V (Pins 2, 3, 6, and 14)
      2. 8.3.2 Midscale (DC) Reference Buffer (Pin 1 and Pin 15)
      3. 8.3.3 Output Power Stage (OPS) (Pins 4, 7, 9, 10, 11, and 12)
        1. 8.3.3.1 Output DC Offset and Drift for the OPS
        2. 8.3.3.2 OPS Harmonic Distortion (HD) Performance
        3. 8.3.3.3 Switch Feedthrough to the OPS
        4. 8.3.3.4 Driving Capacitive Loads
      4. 8.3.4 Digital Control Lines
    4. 8.4 Device Functional Modes
      1. 8.4.1 Full-Signal Path Mode
        1. 8.4.1.1 Internal Connection With Fixed Common-Mode Output Voltage
        2. 8.4.1.2 Internal Connection With Adjustable Common-Mode Output Voltage
        3. 8.4.1.3 External Connection
      2. 8.4.2 Dual-Output Mode
      3. 8.4.3 Differential I/O Voltage Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Applications
        1. 9.1.1.1 High-Frequency, High-Voltage, Dual-Output Line Driver for AWGs
          1. 9.1.1.1.1 Design Requirements
          2. 9.1.1.1.2 Detailed Design Procedure
          3. 9.1.1.1.3 Application Curves
        2. 9.1.1.2 High-Voltage Pulse-Generator
          1. 9.1.1.2.1 Design Requirements
          2. 9.1.1.2.2 Detailed Design Procedure
          3. 9.1.1.2.3 Application Curves
        3. 9.1.1.3 Single-Supply, AC-Coupled, Piezo Element Driver
          1. 9.1.1.3.1 Detailed Design Procedure
        4. 9.1.1.4 Output Common-Mode Control Using the Midscale Buffer as a Level Shifter
          1. 9.1.1.4.1 Detailed Design Procedure
        5. 9.1.1.5 Differential I/O Driver With independent Common-Mode Control
          1. 9.1.1.5.1 Detailed Design Procedure
  10. 10Power Supply Recommendations
    1. 10.1 Thermal Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 TINA-TI (Free Software Download)
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Electrical Characteristics: D2S + OPS

at +VCC = 6.0 V, –VCC = –6.0 V, 25-Ω D2S source impedance, D2S input VIC = 0.25 V, internal path selected to OPS (PATHSEL ≤ 0.7 V or floated), VREF = GND, combined AV = 5 V/V, D2S RLOAD= 200 Ω, RF = 249 Ω(1), RG = 162 Ω (OPS AV = 2.5 V/V), OPS enabled (DISABLE ≤ 0.7 V or floated), OPS RLOAD = 100 Ω, and TJ ≈ 25°C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNITTEST LEVEL (2)
AC PERFORMANCE(4)
Small-signal bandwidth (SSBW)VOUT = 100 mVPP, peaking < 1.5 dB650MHzC
Large-signal bandwidth (LSBW)VOUT = 5 VPP270MHzC
Bandwidth for 0.2-dB flatnessVOUT = 2 VPP110MHzC
Slew rate(3)VOUT = 8-V step3000V/µsC
Overshoot and undershootInput tr = 1 ns, VOUT = 5-V step4%C
Rise and fall timeInput tr = 1 ns, VOUT = 5-V step1.7nsC
Settling time to 0.1%Input tr = 1 ns, VOUT = 5-V step25nsC
2nd-order harmonic distortion (HD2)f = 20 MHz, VOUT= 5 VPP–66dBcC
3rd-order harmonic distortion (HD3)f = 20 MHz, VOUT= 5 VPP–68dBcC
Output voltage noisef > 200 kHz, AV = 5 V/V33nV/√ HzC
DC PERFORMANCE(4)
Total gain D2S to OPS output(1)0.1% tolerance external resistors, dc, ±100-mV output test4.925.025.12V/VA
POWER SUPPLY (Combined D2S, OPS, and Midscale Reference Buffer)
Supply current±6-V supplies32.734.539mAA
Supply current temperature coefficientTJ = 0°C to 100°C±5µA/°CC
(1) Output power stage includes an internal 18.5-kΩ feedback resistor. This internal resistor, in parallel with an external 249-Ω RF and 162-Ω RG, results in a gain of 2.5 V/V after including a nominal gain loss of 0.9935 V/V due to the input buffer and loop-gain effects.
(2) Test levels (all values set by characterization and simulation): (A) 100% tested at TA≈ TJ≈ 25°C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
(3) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (Vpeak / √ 2) × 2π × f–3dB.
(4) Output measured at pin 11.