SBOS780 Data sheet

SBOS780C March 2016 – June 2021 THS3215

PRODUCTION DATA

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Mechanical Data (Package|Pins)

RGV|16
- MPQF121F

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6.6 Electrical Characteristics: OPS

at +V_CC = 6.0 V, –V_CC = –6.0 V, 25-Ω D2S source impedance, D2S input common-mode voltage (V_IC) = 0.25 V, V_REF = GND, R_F = 249 Ω⁽¹⁾, R_G = 162 Ω, A_V = 2.5 V/V, OPS R_LOAD = 100 Ω, OPS enabled (DISABLE ≤ 0.7 V or floated), external OPS input selected (PATHSEL ≥ 1.3 V), and T_J ≈ 25°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT	TEST LEVEL ⁽²⁾
AC PERFORMANCE ⁽⁴⁾
	Small-signal bandwidth (SSBW)	V_OUT = 100 mV_PP, peaking < 2.0 dB		700		MHz	C
	Large-signal bandwidth (LSBW)	V_OUT = 5 V_PP		270		MHz	C
	Bandwidth for 0.2-dB flatness	V_OUT = 5 V_PP		110		MHz	C
	Slew rate⁽³⁾	V_OUT = 5-V step		3000		V/µs	C
	Overshoot and undershoot	Input t_r = 1 ns, V_OUT = 5-V step		4%			C
	Rise and fall time	Input t_r = 1 ns, V_OUT = 5-V step		1.7		ns	C
	Settling time to 0.1%	Input t_r = 1 ns, V_OUT = 5-V step		25		ns	C
	2nd-order harmonic distortion (HD2)	f = 20 MHz, V_OUT= 5 V_PP		–66		dBc	C
	3rd-order harmonic distortion (HD3)	f = 20 MHz, V_OUT= 5 V_PP		–68		dBc	C
	Noninverting input voltage noise	f > 200 kHz		2.7		nV/√ Hz	C
	Noninverting input current noise	f > 200 kHz		1.3		pA/√ Hz	C
	Inverting input current noise	f > 200 kHz		18		pA/√ Hz	C
	Closed-loop ac output impedance	f = 20 MHz		0.25		Ω	C
DC PERFORMANCE ⁽⁴⁾
	Open-loop transimpedance gain⁽¹⁾	V_OUT = ±1 V, R_LOAD= 500-Ω	800	1700		kΩ	A
	Closed-loop gain	0.1% external R_F and R_G resistors	2.495	2.515	2.53	V/V	A
INPUT
	External input offset voltage (pin 9 to pin 12)	T_J ≈ 25°C	–12	±2.5	12	mV	A
		T_J = 0°C to 70°C	–13		12.5	mV	B
		T_J = –40°C to +125°C	–14.1		13.7	mV	B
	External input offset voltage drift (pin 9 to pin 12)	T_J = –40°C to +125°C	–3	–12	–21	µV/°C	B
	Internal input offset voltage (pin 6 to pin 12)	T_J ≈ 25°C	–15	±2.5	15	mV	A
		T_J = 0°C to 70°C	–15.7		15.4	mV	B
		T_J = –40°C to +125°C	–16.6		16	mV	B
	Internal input offset voltage drift (pin 6 to pin 12)	T_J = –40°C to +125°C	–3	–10	–16	µV/°C	B
	External to internal input offset voltage match		–7	±1.2	7	mV	C
	External noninverting input bias current (pin 9)⁽⁵⁾	T_J ≈ 25°C	–5	±5	15	µA	A
		T_J = 0°C to 70°C	–5		15.2	µA	B
		T_J = –40°C to +125°C	–5.2		15.4	µA	B
	External noninverting input bias current drift (pin 9)	T_J = –40°C to +125°C	0	2	3.3	nA/°C	B
	Inverting input bias current – either input selected⁽⁵⁾	T_J ≈ 25°C	–75	±5	75	µA	A
		T_J = 0°C to 70°C	–39		37	µA	B
		T_J = –40°C to +125°C	–43.5		40.5	µA	B
	Inverting input bias current drift	T_J = –40°C to +125°C	–15	–50	–85	nA/°C	B
	Input headroom to either supply			2.6	3.0	V	A
	Common-mode rejection ratio (CMRR)	±3.4-V input range	45	53		dB	A
	Noninverting input resistance		16	18.5	22.4	kΩ	A
	Noninverting input capacitance			3.3		pF	C
	Open-loop inverting input impedance			74		Ω	C
OUTPUT⁽⁶⁾
	Output voltage headroom to either supply	R_LOAD = 500 Ω, T_J ≈ 25°C	1.3	1.4	1.6	V	A
	Output voltage headroom to either supply	R_LOAD = 500 Ω, T_J = –40°C to +125°C			1.8	V	B
	Linear output current	±1.7 V into 20-Ω R_LOAD	75	90		mA	A
	Peak output current	±2.6-V into 20-Ω R_LOAD	120	140		mA	A
	DC output impedance	0-V output, load current = ±40 mA		0.05		Ω	C
	Internal feedback resistor, R_F	Between pins 11 and 12	16	18.5	22.4	kΩ	A
PATHSEL (Pin 4; Logic Reference = Pin 7 = GND)
	Input low logic level	Internal path selected	0.7	0.9		V	A
	Input high logic level	External input selected at VIN pin		0.9	1.3	V	A
	Input voltage range		–0.5		+V_CC	V	A
	PATHSEL voltage when floated	Internal input from D2S selected	0	20	40	mV	A
	Input pin bias current⁽⁷⁾	0-V input	0		15	µA	A
	Input pin bias current⁽⁷⁾	3.3-V input	–150		–250	µA	A
	Input pin impedance			18 \|\| 1.5		kΩ \|\| pF	C
	Switching time	To 1% of final value		80		ns	C
	Input switching glitch	Both inputs at GND		50		mV	C
	Deselected input dc isolation	± 2-V input	70	80		dB	A
	Deselected input ac isolation	2 V_PP, at 20-MHz input	55	65		dB	C
DISABLE (Pin 10; Logic Reference = Pin 7 = GND)
	Input low logic level		0.7	0.9		V	A
	Input high logic level			0.9	1.3	V	A
	Shutdown control voltage range		–0.5		+V_CC	V	B
	Shutdown voltage when floated	Output stage enabled	0	20	40	mV	A
	Input pin bias current⁽⁷⁾	0-V input	0		4	µA	A
	Input pin bias current⁽⁷⁾	3.3-V input	–150		–250	µA	A
	Input pin impedance			18 \|\| 1.5		kΩ \|\| pF	C
	Switching time (turn on or off)	To 10% of final value		200		ns	C
	Shutdown dc isolation (either input)	±2-V input	70	80		dB	A
	Shutdown ac isolation (either input)	2 V_PP at 20-MHz input	55	65		dB	C
POWER SUPPLY
	Supply current (OPS only)	±6-V supplies	9.6	10.8	12	mA	A
	Disabled supply current in OPS	±6-V supplies	1.5	2	2.9	mA	B
	Logic reference current at pin 7⁽⁷⁾	Pins 4, 7, and 10 held at 0 V	200	280	380	µA	A
	Positive power-supply rejection ratio (+PSRR)	Referred to input	55	60		dB	A
	Negative power-supply rejection ratio (–PSRR)	Referred to input	53	56		dB	A

(1) Output power stage includes an internal 18.5-kΩ feedback resistor. This internal resistor, in parallel with an external 249-Ω R_F and 162-Ω R_G, results in a gain of 2.5 V/V after including a nominal gain loss of 0.9935 V/V due to the input buffer and loop-gain effects.

(2) Test levels (all values set by characterization and simulation): (A) 100% tested at T_A≈ T_J≈ 25°C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information. DC limits tested with no self-heating. Add internal self heating to T_A for T_J.

(3) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (Vpeak / √ 2) × 2π × f_–3dB.

(4) Output measured at pin 11.

(5) Currents out of pin treated as a positive polarity.

(6) Output measured at pin 11.

(7) Currents out of pin treated as a positive polarity.