An easy way to insert a dc offset into the signal channel (without sacrificing any of the DAC dynamic range) is to apply the desired offset at VMID_IN (pin 1) and use it to bias VREF (pin 14) and VIN+ (pin 9). An example is shown in Figure 9-10. This example shows a relatively low maximum differential input of 1 V_PP on any compliance voltage required by the DAC. Other configuration options include:

1. The D2S output is offset using a dc input at VMID_IN. Although shown here as ±2 V, the dc range expands to ±3.5 V when using ±7.5 V supplies.
2. Connect VMID_OUT (pin 15) to the VREF input to place the D2S output at the dc offset voltage along with a gain of 2 V/V version of the differential input voltage. The stated range of ±2 V, along with the ±0.5 V out of the upper input buffer, requires a peak output current from VMID_OUT of 2.5 V / 150 Ω = 16.7 mA. This value is well below the rated minimum linear output current of 40 mA for the midscale buffer.
3. The dc offset voltage is then applied to the external OPS non-inverting input, VIN+. Connecting the circuit in this manner results in no additional dc gain for the dc offset between the D2S and OPS outputs, while continuing to retain the signal gain of the OPS configured as an inverting amplifier. The values of R_F and R_G in this application example are derived from Table 8-3. The OPS is setup for a gain of –4 V/V in this example. Using the resistor values from Table 8-3 results in the widest bandwidth for the OPS; however, the R_G = 51.1 Ω resistor presents a heavy load to the D2S output. In such cases, the OPS external resistors can be scaled up to reduce the D2S output load, but at the expense of reduced OPS bandwidth.
4. No filtering is shown in this example; however, introducing filtering in the OPS R_G path is certainly possible. In such cases, the R_G element is also the filter termination resistor. Filtering adds insertion loss that can be recovered by adjusting the OPS gain setting.