The THS3217 combines the key signal-chain components required to interface with a complementary-current output, digital-to-analog converter (DAC). The flexibility provided by this two-stage amplifier system delivers the low distortion, dc-coupled, differential to single-ended signal processing required by a wide range of systems. The input stage buffers the DAC resistive termination, and converts the signal from differential to single-ended with a fixed gain of 2 V/V. The differential to single-ended output is available externally for direct use, and can also be connected through an RLC filter or attenuator to the input of an internal output power stage (OPS). The wideband, current-feedback, output power stage provides all pins externally for flexible gain setting.
An internal 2×1 multiplexer (mux) to the output power stage noninverting input provides an easy means to select between the internal differential-to-single-ended stage (D2S) output or an external input.
An optional on-chip midsupply buffer provides a wideband, low-output-impedance source for biasing during single-supply operation through the signal-path stages. This feature provides very simple biasing for single-supply, ac-coupled applications operating up to a maximum 15.8-V supply. An external input to this buffer allows for a dc error-correction loop, or a simple output dc offset feature.
A companion device, the THS3215, provides the same functional features at lower quiescent power and bandwidth. The THS3217 and the THS3215 support the emerging high-speed Texas Instruments DACs for AWG applications, such as the DAC38J82.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
THS3217 | VQFN (16) | 4.00 mm × 4.00 mm |
Changes from A Revision (February 2016) to B Revision
Changes from * Revision (February 2016) to A Revision
DEVICE | SMALL-SIGNAL BANDWIDTH 0.1 VPP (AV = 5 V/V)(1) |
LARGE-SIGNAL BANDWIDTH 5VPP (AV = 5 V/V) |
QUIESCENT CURRENT, Icc (±6-V SUPPLIES) |
TOTAL HARMONIC DISTORTION (5 VPP, RLOAD = 100 Ω, 20 MHz) |
CONTINUOUS OUTPUT CURRENT | PEAK OUTPUT CURRENT |
---|---|---|---|---|---|---|
THS3217 | 800 MHz | 500 MHz | 55 mA | –60 dBc | 110 mA | 175 mA |
THS3215 | 350 MHz | 250 MHz | 35 mA | –50 dBc | 80 mA | 125 mA |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VMID_IN | Input | DC reference buffer input |
2 | +IN | Input | Positive signal input to D2S |
3 | –IN | Input | Negative signal input to D2S |
4 | PATHSEL | Input | Internal SPDT switch control: low selects the internal path, and high selects the external path |
5 | –VCC2(1) | Power | Negative supply for input stage |
6 | VO1 | Output | D2S external output |
7 | GND | Power | Ground for control pins reference |
8 | –VCC1(1) | Power | Negative supply for output stage |
9 | VIN+ | Input | External OPS noninverting input |
10 | DISABLE | Input | Output power stage shutdown control: low enables the OPS, and high disables the OPS |
11 | VOUT | Output | OPS output |
12 | VIN– | Input | OPS inverting input |
13 | +VCC1(1) | Power | Positive supply for output stage |
14 | VREF | Input | DC offsetting input to D2S |
15 | VMID_OUT | Output | DC reference buffer output |
16 | +VCC2(1) | Power | Positive supply for input stage |
Thermal Pad | — | Connect the thermal pad to GND for single-supply and split-supply operation. See Thermal Considerations section for more information. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | Supply, +VCC – (–VCC) | 16.2 | V | |
Input/output | (–VCC) – 0.5 | (+VCC) + 0.5 | ||
Differential input voltage (IN+ – IN–) | ±8 | |||
Current | Continuous input current (IN+, IN–, VMID_IN, VIN+, VIN–)(2) | ±10 | mA | |
Continuous output current(2) | ±30 | |||
Temperature | Operating, TA | –55 | 105 | °C |
Junction, TJ | –45 | 150 | ||
Storage, Tstg | –65 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±1500 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
+VCC | Positive supply voltage | 4 | 6 | 7.9 | V |
–VCC | Negative supply voltage | –4 | –6 | –7.9 | V |
TA | Operating free-air temperature | –40 | 25 | 85 | °C |
THERMAL METRIC(1) | THS3217 | UNIT | |
---|---|---|---|
RGV (VQFN) | |||
16 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 45 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 45 | °C/W |
RθJB | Junction-to-board thermal resistance | 22 | °C/W |
ψJT | Junction-to-top characterization parameter | 1 | °C/W |
ψJB | Junction-to-board characterization parameter | 22 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 4 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | TEST LEVEL (1) | |
---|---|---|---|---|---|---|---|
AC PERFORMANCE (Power Stage Disabled: DISABLE pin ≥ 1.3 V) (5) | |||||||
Small-signal bandwidth (SSBW) | VOUT = 250 mVPP, peaking < 1.0 dB | 800 | MHz | C | |||
Large-signal bandwidth (LSBW) | VOUT = 2 VPP | 500 | MHz | C | |||
Bandwidth for 0.2-dB flatness | VOUT = 2 VPP | 250 | MHz | C | |||
Slew rate(2) | VOUT = 4-V step | 2500 | V/µs | C | |||
Over- and undershoot | Input tr = 1 ns, VOUT = 2-V step | 6% | C | ||||
Rise and fall time | Input tr = 1 ns, VOUT = 2-V step | 1.2 | ns | C | |||
Settling time to 0.1% | Input tr = 1 ns, VOUT = 2-V step | 5 | ns | C | |||
2nd-order harmonic distortion (HD2) | f = 20 MHz, VOUT= 2 VPP | –68 | dBc | C | |||
3rd-order harmonic distortion (HD3) | f = 20 MHz, VOUT= 2 VPP | –86 | dBc | C | |||
Output voltage noise | f > 200 kHz | 18 | nV/√Hz | C | |||
Input current noise (each input) | f > 200 kHz | 2.0 | pA/√Hz | C | |||
Output impedance | f = 20 MHz | 0.8 | Ω | C | |||
DC PERFORMANCE (5) | |||||||
Differential to single-ended gain | ±100-mV output | 1.975 | 2.0 | 2.025 | V/V | A | |
Differential to single-ended gain drift | TJ = –40°C to +125°C | –20 | –24 | ppm/°C | B | ||
VREF input pin gain | Differential inputs = 0 V, VREF = ±100 mV |
0.985 | 1.0 | 1.015 | V/V | A | |
VREF input pin gain drift | TJ = –40°C to +125°C | –70 | –95 | ppm/°C | B | ||
Output offset voltage | TJ = 25°C | –35 | ±8 | 35 | mV | A | |
TJ = 0°C to 70°C | –43 | 40 | mV | B | |||
TJ = –40°C to +125°C | –54 | 47 | mV | B | |||
Output offset voltage drift | TJ = –40°C to +125°C | -40 | –115 | –190 | µV/°C | B | |
Input bias current – each input(3) | TJ = 25°C | –4 | ±2 | 4 | µA | A | |
TJ = 0°C to 70°C | –4.2 | 4.2 | µA | B | |||
TJ = –40°C to +125°C | –4.3 | 4.5 | µA | B | |||
Input bias current drift | TJ = –40°C to +125°C | 1 | 3 | 5 | nA/°C | B | |
Input offset current | TJ = 25°C | –400 | ±50 | 400 | nA | A | |
TJ = 0°C to 70°C | –700 | 940 | nA | B | |||
TJ = –40°C to +125°C | –1180 | 1600 | nA | B | |||
Input offset current drift | TJ = –40°C to +125°C | –12 | ±1 | 12 | nA/°C | B | |
INPUTS(4) | |||||||
Common-mode input negative supply headroom | TJ = 25°C | 1.8 | 1.9 | V | A | ||
TJ = –40°C to +85°C | 2.0 | V | B | ||||
Common-mode input positive supply headroom | TJ = 25°C | 1.3 | 1.4 | V | A | ||
TJ = –40°C to +125°C | 1.5 | V | B | ||||
Common-mode rejection ratio (CMRR) | –1 V ≤ VIC ≤ 3 V | 47 | 55 | dB | A | ||
Input impedance differential mode | VCM = 0 V | 50 || 2.4 | kΩ || pF | C | |||
Input impedance common mode | VCM = 0 V | 90 || 2.4 | kΩ || pF | C | |||
OUTPUT(6) | |||||||
Output voltage headroom to either supply | TJ = 25°C | 1.1 | 1.35 | 1.55 | V | A | |
TJ = –40°C to +125°C | V | B | |||||
Output current drive | TJ = 25°C, ±1.16 VPP, RLOAD = 20 Ω | 50 | 70 | mA | A | ||
DC Output Impedance | Load current = ±20 mA | 0.2 | 0.45 | Ω | A | ||
POWER SUPPLY (D2S Stage + Midsupply Buffer Only; Output Power Stage Disabled: DISABLE pin ≥ 1.3 V) | |||||||
Bipolar-supply operating range | ±4.0 | ±6.0 | ±7.9 | V | A | ||
Single-supply operating range | 8 | 12 | 15.8 | V | B | ||
Supply current | ±6-V supplies | 31 | 34 | 36 | mA | A | |
Supply current temperature coefficient | 7 | µA/°C | C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | TEST LEVEL (2) | |
---|---|---|---|---|---|---|---|
AC PERFORMANCE (4) | |||||||
Small-signal bandwidth (SSBW) | VOUT = 100 mVPP, peaking < 1.0 dB | 950 | MHz | C | |||
Large-signal bandwidth (LSBW) | VOUT = 5 VPP | 500 | MHz | C | |||
Bandwidth for 0.2-dB flatness | VOUT = 5 VPP | 110 | MHz | C | |||
Slew rate(3) | VOUT = 5-V step | 5500 | V/µs | C | |||
Over- and undershoot | Input tr = 1 ns, VOUT = 5-V step | 8% | C | ||||
Rise and fall time | Input tr = 1 ns, VOUT = 5-V step | 1.1 | ns | C | |||
Settling time to 0.1% | Input tr = 1 ns, VOUT = 5-V step | 5 | ns | C | |||
2nd-order harmonic distortion (HD2) | f = 20 MHz, VOUT= 5 VPP | –69 | dBc | C | |||
3rd-order harmonic distortion (HD3) | f = 20 MHz, VOUT= 5 VPP | –73 | dBc | C | |||
Noninverting input voltage noise | f > 200 kHz | 3.2 | nV/√Hz | C | |||
Noninverting input current noise | f > 200 kHz | 2.8 | pA/√Hz | C | |||
Inverting input current noise | f > 200 kHz | 30 | pA/√Hz | C | |||
Closed-loop ac output impedance | f = 20 MHz | 0.40 | Ω | C | |||
DC PERFORMANCE (4) | |||||||
Open-loop transimpedance gain(1) | VOUT = ±1 V, RLOAD= 500-Ω | 600 | 1200 | kΩ | A | ||
Closed-loop gain | 0.1% external RF and RG resistors | 2.495 | 2.515 | 2.53 | V/V | A | |
INPUT | |||||||
External input offset voltage (pin 9 to pin12) | TJ = 25°C | –12 | ±2.5 | 12 | mV | A | |
TJ = 0°C to 70°C | –20 | 17 | mV | B | |||
TJ = –40°C to +125°C | –31 | 24 | mV | B | |||
External input offset voltage drift (pin 9 to pin12) | TJ = –40°C to +125°C | -45 | –115 | –190 | µV/°C | B | |
Internal input offset voltage (pin 6 to pin 12) | TJ = 25°C | –12 | ±2.5 | 12 | mV | A | |
TJ = 0°C to 70°C | –23 | 18 | mV | B | |||
TJ = –40°C to +125°C | –35 | 27 | mV | B | |||
Internal input offset voltage drift (pin 6 to pin 12) | TJ = –40°C to +125°C | –70 | –150 | –235 | µV/°C | B | |
External to internal input offset voltage match | TJ = 25°C | ±1.2 | mV | C | |||
External noninverting input bias current (pin 9)(5) | TJ = 25°C | –5 | ±5 | 15 | µA | A | |
TJ = 0°C to 70°C | –5.2 | 15.4 | µA | B | |||
TJ = –40°C to +125°C | –5.6 | 15.9 | µA | B | |||
External noninverting input bias current drift (pin 9) | TJ = –40°C to +125°C | –3 | 3 | 9 | nA/°C | B | |
Inverting input bias current – either input selected(5) | TJ = 25°C | –40 | ±5 | 40 | µA | A | |
TJ = 0°C to 70°C | –51 | 46 | µA | B | |||
TJ = –40°C to +125°C | –65 | 56 | µA | B | |||
Inverting input bias current drift | TJ = –40°C to +125°C | –250 | –120 | –10 | nA/°C | B | |
Input headroom to either supply | TJ = 25°C | 2.6 | 3.0 | V | A | ||
Common-mode rejection ratio (CMRR) | 47 | 49 | dB | A | |||
Noninverting input resistance | 17.6 | 18.5 | 22.4 | kΩ | A | ||
Noninverting input capacitance | 3.3 | pF | C | ||||
Open-loop inverting input impedance | 42 | Ω | C | ||||
OUTPUT(6) | |||||||
Output voltage headroom to either supply | RLOAD = 500 Ω | 1.1 | 1.3 | 1.4 | V | A | |
Linear output current | TJ = 25°C, ±2.5 V into 26-Ω RLOAD | 95 | 120 | mA | A | ||
Peak output current | 0-V output, RLOAD < 0.2 Ω | 135 | 170 | mA | A | ||
DC output impedance | 0-V output, load current = ±40 mA | 0.05 | 0.10 | Ω | A | ||
Internal RF | 17.6 | 18.5 | 22.4 | kΩ | A | ||
PATHSEL (Pin 4; Logic Reference = Pin 7 = GND) | |||||||
Input low logic level | Internal path selected | 0.7 | 0.9 | V | A | ||
Input high logic level | External input selected at VIN (pin 9) | 0.9 | 1.3 | V | A | ||
Input voltage range | –0.5 | +VCC | V | A | |||
PATHSEL voltage when floated | Internal input from D2S selected | 0 | 20 | 40 | mV | A | |
Input pin bias current(7) | 0-V input | 0 | 4 | µA | A | ||
3.3-V input | –150 | –250 | µA | A | |||
Input pin impedance | 18 || 1.5 | kΩ || pF | C | ||||
Switching time | To 1% of final value | 80 | ns | C | |||
Input switching glitch | Both inputs at GND | 50 | mV | C | |||
Deselected input dc isolation | ± 2-V input | 70 | 80 | dB | A | ||
Deselected input ac isolation | 2 VPP, at 20-MHz input | 55 | 65 | dB | C | ||
DISABLE (Pin 10; Logic Reference = Pin 7 = GND) | |||||||
Input low logic level | 0.7 | 0.9 | V | A | |||
Input high logic level | 0.9 | 1.3 | V | A | |||
Shutdown control voltage range | –0.5 | +VCC | V | B | |||
Shutdown voltage when floated | Output stage enabled | 0 | 20 | 40 | mV | A | |
Input pin bias current(7) | 0-V input | 0 | 4 | µA | A | ||
3.3-V input | –150 | –250 | µA | A | |||
Input pin impedance | 18 || 1.5 | kΩ || pF | C | ||||
Switching time (turn on or off) | To 10% of final value | 200 | ns | C | |||
Shutdown dc isolation (either input) | ±2-V input | 70 | 80 | dB | A | ||
Shutdown ac isolation (either input) | 2 VPP at 20-MHz input | 55 | 65 | dB | C | ||
POWER SUPPLY | |||||||
Bipolar-supply operating range | ±4.0 | ±6.0 | ±7.9 | V | A | ||
Single-supply operating range | 8 | 12 | 15.8 | V | B | ||
Supply current (OPS only) | ±6-V supplies | 18.5 | 21 | 24.5 | mA | A | |
Disabled supply current in OPS | ±6-V supplies | 2.0 | 2.4 | 3.0 | mA | C | |
Logic reference current at pin 7(7) | Pins 4, 7, and 10 held at 0 V | 200 | 280 | 380 | µA | A |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | TEST LEVEL (2) | |
---|---|---|---|---|---|---|---|
AC PERFORMANCE(4) | |||||||
Small-signal bandwidth (SSBW) | VOUT = 100 mVPP, peaking < 1.5 dB | 800 | MHz | C | |||
Large-signal bandwidth (LSBW) | VOUT = 5 VPP | 500 | MHz | C | |||
Bandwidth for 0.2-dB flatness | VOUT = 2 VPP | 100 | MHz | C | |||
Slew rate(3) | VOUT = 8-V step | 5000 | V/µs | C | |||
Over- and undershoot | Input tr = 1 ns, VOUT = 5-V step | 8% | C | ||||
Rise and fall time | Input tr = 1 ns, VOUT = 5-V step | 1.1 | ns | C | |||
Settling time to 0.1% | Input tr = 1 ns, VOUT = 5-V step | 7 | ns | C | |||
2nd-order harmonic distortion (HD2) | f = 20 MHz, VOUT= 5 VPP | –60 | dBc | C | |||
3rd-order harmonic distortion (HD3) | f = 20 MHz, VOUT= 5 VPP | –75 | dBc | C | |||
Output voltage noise | f > 200 kHz | 45 | nV/√Hz | C | |||
DC PERFORMANCE(4) | |||||||
Total gain D2S to OPS output(1) | 0.1% tolerance, dc, ±100-mV output test | 4.92 | 5.02 | 5.12 | V/V | A | |
POWER SUPPLY (Combined D2S, OPS, and Midscale Reference Buffer) | |||||||
Bipolar-supply operating range | ±4.0 | ±6.0 | ±7.9 | V | A | ||
Single-supply operating range | 8 | 12 | 15.8 | V | B | ||
Supply current | ±6-V supplies | 51 | 54 | 57 | mA | A | |
Supply current temperature coefficient | 10 | µA/°C | C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | TEST LEVEL (1) | |
---|---|---|---|---|---|---|---|
AC PERFORMANCE (Output measured at pin 15) | |||||||
Small-signal bandwidth (SSBW) | VOUT = 100 mVPP | 400 | MHz | C | |||
Large-signal bandwidth (LSBW) | VOUT = 1 VPP | 110 | MHz | C | |||
Slew rate(2) | VOUT = 4-V step | 250 | V/µs | C | |||
Input voltage noise | f > 200 kHz | 4.4 | nV/√Hz | C | |||
Input current noise | f > 200 kHz | 2.3 | pA/√Hz | C | |||
AC output impedance | f = 20 MHz | 1.0 | Ω | C | |||
DC AND I/O PERFORMANCE (RS = 25 Ω, and output measured at pin 15, unless otherwise noted) | |||||||
Buffer gain | VI = ±1 V, RLOAD = 200 Ω | .9985 | 0.999 | 1.001 | V/V | A | |
Buffer gain drift | TJ = –40°C to +125°C | –1.5 | –2.0 | ppm/°C | B | ||
Output offset from midsupply | Input floating, pin 1 open | –120 | 30 | 70 | mV | A | |
Output offset voltage | TJ = 25°C, input driven to 0 V from 0-Ω source | –1.0 | 4.0 | 15 | mV | A | |
Input offset voltage drift | TJ = –40°C to +125°C, input driven to 0 V | –4 | 3 | 10 | µV/°C | B | |
Input bias current(3) | TJ = 25°C | –15 | ±1 | 15 | µA | A | |
Input bias current drift | TJ = –40°C to +125°C | –8 | –2 | 3 | nA/°C | B | |
Input/output headroom to either supply | TJ = 25°C, gain change < 1% | 1.1 | 1.4 | V | A | ||
Input impedance | Internal 50-kΩ divider resistors to each supply | 22 || 1.5 | kΩ || pF | C | |||
Linear output current into resistive load | ±2.25 V into 36 Ω | 40 | 65 | mA | A | ||
DC output impedance | Load current = ±30 mA | 0.21 | Ω | C |
26 units shown |
VOUT = 5 VPP |
Test frequency = 20 MHz |
25-Ω source impedance on each D2S input |
VOUT = 5 VPP |
Test frequency = 20 MHz |
VOUT = 250 mVPP |
RLOAD = 200 Ω |
30 units shown |
±1-V output pulse |
25-Ω D2S source impedance on each input |
VOUT = 2 VPP |
RLOAD = 200 Ω |
±1-V output pulse |
VOUT = 100 mVPP, see Table 2 for RF values vs gain |
VOUT = 5 VPP |
VOUT = 5 VPP |
±100-kHz tone separation, output voltage for each tone |
30 units shown |
RF = 205 Ω, AV = 5 V/V, VOUT = 10 VPP, see Figure 43 for RS value |
VOUT = 5 VPP |
VOUT = 5 VPP |
±100-kHz tone separation, output voltage for each tone |
Output swing with better than 0.1% linearity |
±4.5-V input triangular wave, OPS AV = 2.5 V/V |
RF = 205 Ω, AV = 5 V/V, VOUT = 10 VPP, see Figure 43 for RS value |
RLOAD = 150 Ω in parallel with CLOAD, see the Midscale Buffer ROUT Versus CLOAD Measurement section for circuit setup |
VOUT = 100 mVPP, RLOAD = 150 Ω in parallel with CLOAD, see Midscale Buffer ROUT Versus CLOAD Measurement for circuit setup |
D2S Inputs: IN+ = IN– = GND, OPS input: VIN+ = 1 V |
D2S inputs: IN+ = IN– = GND, OPS input: VIN+ = 1 V |
PATHSEL = high, OPS input: VIN+ = 1 VPP , 10-MHz sine wave |
PATHSEL = high, OPS input: VIN+ = 1 V |
30 units shown |
29 units shown |
30 units shown |
30 units from –40°C to +125°C |
29 units from –40°C to +125°C |
30 units from –40°C to +125°C |
The THS3217 comprises three blocks of high-performance amplifiers. Each block requires both frequency-response and step-response characterization. The midscale buffer and OPS use standard, single-ended I/O test methods with network analyzers, pulse generators, and high-speed oscilloscopes. The differential to single-ended input stage (D2S) requires a wideband differential source for test purposes. All ac characterization tests were performed using the THS3217 evaluation module (EVM), the THS3217EVM, which offers many configuration options. For most of the D2S-only tests, the OPS was disabled. Figure 67 shows a typical configuration for an ac frequency-response test of the D2S.
The THS3217EVM includes unpopulated, optional, passive elements at the D2S inputs to implement a differential filter. These elements were not used in the D2S characterization and the two input pins were terminated to ground through 49.9-Ω resistors. DC test points are provided through 10-kΩ or 20-kΩ resistors on all THS3217 nodes. Figure 67 also shows the output network used to emulate a 200-Ω load resistance (RLOAD) while presenting a 50-Ω source back to the D2S output pin. The R3 (= 169 Ω) and R4 (= 73.2 Ω) resistors combine with the 50-Ω network analyzer input impedance to present a 200-Ω load at VO1 (pin 6), The impedance presented from the input of the network analyzer back to the D2S output (VO1, pin 6) is 50-Ω. The 16.5-dB insertion loss intrinsic to this dc-coupled impedance network is removed from the characterization curves. The VREF pin was connected to GND for all the tests.
For D2S and full-signal path (D2S + OPS) characterization, the LMH3401, a very wideband, dc-coupled, single-ended to differential amplifier was used. The LMH3401EVM was used as an interface between a single-ended source and the differential input required by the D2S, shown in Figure 68. The LMH3401 provides an input impedance of 50 Ω, and converts a single-ended input to a differential output driving through 50-Ω outputs on each side to what is a 50-Ω termination at each input of the THS3217 D2S.
The LMH3401 provides 7-GHz bandwidth with 0.1-dB flatness through 700 MHz. From the single-ended matched input (using active match through an internal 12.5-Ω resistor), the LMH3401 produces a differential output with 16-dB gain to the internal output pins. Building out to a 50-Ω source by adding external 40.2-Ω resistors on both differential outputs in series with the internal 10-Ω resistor, results in a net gain of 10 dB to the matched 50-Ω load on the THS3217EVM.
The maximum output swing test for the D2S stage is 4 VPP (see Figure 15 and Figure 16). With a fixed gain of 2 V/V, the tests in Figure 15 and Figure 16 require a 2-VPP differential input. In order to achieve the 2-VPP differential swing at the D2S inputs, the LMH3401 internal outputs must drive a 4-VPP differential signal around the VOCM of the LMH3401. This LMH3401 single-to-differential preamplifier is normally operated with ±2.5-V supplies, and VOCM set to ground. Under these conditions, the LMH3401 supports ±1.4 V on each internal output pin; well beyond the maximum required for THS3217 D2S characterization of ±1 V.
The output of the LMH3401EVM connects directly to the Vin+ (J1) and Vin- (J2) SMA connectors on the THS3217EVM, as shown in Figure 67. The physical spacing of the SMA connectors has been set to line up for a direct (no cabling) connection between the two different EVMs using SMA barrels. For THS3217 designs that must be evaluated before any DAC connection, consider using the LMH3401EVM as a gain of 10 dB, single-to-differential interface to the inputs of the D2S stage. This setup allows single-ended sources to generate differential output signals through the combined LMH3401EVM to THS3217EVM configuration. The D2S, small-signal, frequency-response curves over input common-mode voltage (see Figure 13) were generated by adjusting the LMH3401 voltage supplies and maintaining VOCM at midsupply to preserve input headroom on the LMH3401. In order to make single-ended, frequency-response measurements, the configuration shown in Figure 69 was used.
The distortion plots for all stages used a filtered high-frequency function generator to generate a very low-distortion input signal. The LMH3401 interface was used when testing the D2S and the full-signal path (D2S+OPS) harmonic distortion performance. Running the filtered signal through the LMH3401, as shown in Figure 70, provided adequate input signal purity because of the approximately –100-dBc harmonic distortion performance through 100 MHz. In order to test the harmonic-distortion performance of the OPS and midscale buffer, the configuration shown in Figure 71 was used.
All the noise measurements were made using a very low-noise, high-gain bandwidth LMH6629 as a low-noise preamplifier to boost the output noise from the THS3217 before measurement on a spectrum analyzer, as shown in Figure 72. The 0.69-nV/√Hz input-voltage noise specification of the LMH6629 provides flat gain of 20 V/V through 100 MHz with its ultrahigh, 6.3-GHz gain bandwidth product. The D2S and OPS noise was measured with the common-mode voltage at GND.
Output impedance measurement for the three stages under different conditions were performed as a small-signal measurement calibrated to the device pins using an impedance analyzer. Calibrating the measurement to the device pins removes the THS3217EVM parasitic resistance, inductance, and capacitance from the measured data.
Generating a clean, fast, differential-input step for time-domain testing presents a considerable challenge. A multichannel pulse generator with adjustable rise and fall times was used to generate the differential pulse to drive D2S inputs in Figure 21. A high-speed scope was used to digitize the pulse response.
In order to test the forward feedthrough performance of the OPS in the disabled state, the circuit shown in Figure 73 was used. The PATHSEL pin was driven low to select the internal path between the D2S and OPS. A 100-mVPP, swept-frequency, sinusoidal signal was applied at the VREF pin and the output signal was measured at the OPS output pin (VOUT). The transfer function from VREF to the output of the D2S at VO1 has a gain of 0 dB, as shown in Figure 23. The results shown in Figure 57 account for the 6-dB loss due to the doubly-terminated OPS output, and therefore report the forward feedthrough between VOUT and VO1 at different OPS gains. The D2S inputs were grounded through 50-Ω resistors for this test.
In order to test the reverse feedthrough performance of the OPS in its disabled state, the circuit shown in Figure 74 was used. The PATHSEL pin was driven high to select the external path to the OPS noninverting pin, VIN+. A 100-mVPP, swept-frequency, sinusoidal signal was applied at the VIN+ pin and the output signal was measured at the D2S output pin (VO1). The results shown in Figure 58 account for the 16.5-dB loss due to the D2S termination, and the test reports the reverse feedthrough between the VO1 and VIN+ pins. The D2S inputs were grounded through 50-Ω resistors for this test.
For the tests in Figure 53 and Figure 54, the circuit shown in Figure 75 was used. The 150-Ω load circuit configured as shown, provides a 50-Ω path from the network analyzer back to the output of the buffer. As shown in Figure 75, place ROUT below the load capacitor to improve the phase margin for the closed-loop buffer output, while adding 0-Ω dc impedance into the line connected to the VREF pin.